參數(shù)資料
型號： ADM690-ADM695
英文描述： Microprocessor Supervisory Circuits
中文描述： 微處理器監(jiān)控電路
文件頁數(shù)： 2/16頁
文件大?。?/td> 283K
代理商： ADM690-ADM695
ADM690–ADM695–SPECIFICATIONS
Parameter
Min
T yp
Max
Units
T est Conditions/Comments
BAT T ERY BACK UP SWIT CHING
V
CC
Operating Voltage Range
ADM690, ADM691, ADM694, ADM695
ADM692, ADM693
V
BAT T
Operating Voltage Range
ADM690, ADM691, ADM694, ADM695
ADM692, ADM693
V
OUT
Output Voltage
4.75
4.5
5.5
5.5
V
V
2.0
2.0
V
CC
– 0.05
V
CC
– 0.5
V
BAT T
– 0.05 V
BAT T
– 0.02
4.25
4.0
V
V
V
V
V
mA
μ
A
V
CC
– 0.025
V
CC
– 0.25
I
OUT
= 1 mA
I
OUT
≤
100 mA
I
OUT
= 250
μ
A, V
CC
< V
BAT T
– 0.2 V
I
OUT
= 100 mA
V
CC
= 0 V, V
BAT T
= 2.8 V
5.5 V > V
CC
> V
BAT T
+ 0.2 V
T
A
= +25
°
C
V
OUT
in Battery Backup Mode
Supply Current (Excludes I
OUT
)
Supply Current in Battery Backup Mode
Battery Standby Current
(+ = Discharge, – = Charge)
1
0.6
1.95
1
–0.1
–1.0
+0.02
+0.02
μ
A
μ
A
mV
mV
mV
V
mA
μ
A
Battery Switchover T hreshold
V
CC
– V
BAT T
Battery Switchover Hysteresis
BAT T ON Output Voltage
BAT T ON Output Short Circuit Current
70
50
20
Power Up
Power Down
0.3
I
SINK
= 3.2 mA
BAT T ON = V
OUT
= 4.5 V Sink Current
BAT T ON = 0 V Source Current
35
1
0.5
25
RESET AND WAT CHDOG T IMER
Reset Voltage T hreshold
ADM690, ADM691, ADM694, ADM695
ADM692, ADM693
Reset T hreshold Hysteresis
Reset T imeout Delay
ADM690, ADM691, ADM692, ADM693
ADM694, ADM695
Watchdog T imeout Period, Internal Oscillator
4.5
4.25
4.65
4.4
40
4.73
4.48
V
V
mV
35
140
1.0
70
3840
768
50
50
200
1.6
100
70
280
2.25
140
4097
1025
ms
ms
s
ms
Cycles
Cycles
ns
mV
V
V
V
V
μ
A
mA
OSC SEL = HIGH, V
CC
= 5 V, T
A
= +25
°
C
OSC SEL = HIGH, V
CC
= 5 V, T
A
= +25
°
C
Long Period, V
CC
= 5 V, T
A
= +25
°
C
Short Period, V
CC
= 5 V, T
A
= +25
°
C
Long Period
Short Period
V
IL
= 0.4, V
IH
= 3.5 V
I
SINK
= 10
μ
A, V
CC
= 1 V
I
SINK
= 1.6 mA, V
CC
= 4.25 V
I
SOURCE
= 1
μ
A, V
CC
= 5 V
I
SINK
= 1.6 mA, V
CC
= 5 V
I
SOURCE
= 1
μ
A, V
CC
= 4.25 V
Watchdog T imeout Period, External Clock
Minimum WDI Input Pulse Width
RESET
Output Voltage @ V
CC
= +1 V
RESET
,
LOW
LINE
Output Voltage
4
200
0.4
3.5
RESET
,
WDO
Output Voltage
0.4
3.5
1
Output Short Circuit Source Current
Output Short Circuit Sink Current
WDI Input T hreshold
Logic Low
Logic High
WDI Input Current
3
25
25
V
CC
= 5 V
1
0.8
V
V
μ
A
μ
A
3.5
20
–15
50
WDI = V
OUT
, T
A
= +25
°
C
WDI = 0 V, T
A
= +25
°
C
–50
POWER FAIL DET ECT OR
PFI Input T hreshold
PFI Input Current
PFO
Output Voltage
1.25
–25
1.3
±
0.01
1.35
+25
0.4
V
nA
V
V
μ
A
mA
V
CC
= +5 V
I
SINK
= 3.2 mA
I
SOURCE
= 1
μ
A
PFI = Low,
PFO
= 0 V
PFI = High,
PFO
= V
OUT
3.5
1
PFO
Short Circuit Source Current
PFO
Short Circuit Sink Current
3
25
25
CHIP ENABLE GAT ING
CE
IN
T hreshold
0.8
V
V
μ
A
V
V
V
ns
V
IL
V
IH
3.0
CE
IN
Pull-Up Current
CE
OUT
Output Voltage
3
0.4
I
SINK
= 3.2 mA
I
SOURCE
= 3.0 mA
I
SOURCE
= 1
μ
A, V
CC
= 0 V
V
OUT
– 1.5
V
OUT
– 0.05
CE
Propagation Delay
5
9
REV. A
(V
CC
= Full Operating Range, V
BATT
= +2.8 V, T
A
= T
MN
to
T
MAX
unless otherwse noted)
–2–
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