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| 型號： | ADM690-ADM695 |
| 英文描述： | Microprocessor Supervisory Circuits |
| 中文描述： | 微處理器監(jiān)控電路 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 283K |
| 代理商： | ADM690-ADM695 |
ADM690–ADM695
REV. A
–12–
ADM690
ADM692
ADM694
R
2
R
1
PFO
+5V
V
CC
CMOS RAM
POWER
I/O LINE
μ
P NMI
μ
P RESET
μ
P SYSTEM
μ
P POWER
V
OUT
RESET
WDI
GND
PFI
V
BATT
BATTERY
+
0.1
μ
F
Figure 23a. ADM690/ADM692/ADM694 Typical Application
Circuit A
Figure 23b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu-
lator. T his gives an earlier warning of an impending power fail-
ure. It is useful with processors operating at low speeds or
where there are a significant number of housekeeping tasks to be
completed before the power is lost.
ADM690
ADM692
ADM694
R
2
R
1
PFO
7805
INPUT
POWER
V > 8V
+5V
V
CC
CMOS RAM
POWER
I/O LINE
μ
P NMI
μ
P RESET
μ
P SYSTEM
μ
P POWER
V
OUT
RESET
WDI
GND
PFI
V
BATT
0.1
μ
F
BATTERY
0.1
μ
F
Figure 23b. ADM690/ADM692/ADM694 Typical Application
Circuit B
ADM691, ADM693, ADM695
A typical connection for the ADM691/ADM693/ADM695 is
shown in Figure 24. CMOS RAM is powered from V
OUT
. When
5 V power is present this is routed to V
OUT
. If V
CC
fails then
V
BAT T
is routed to V
OUT
. V
OUT
can supply up to 100 mA from
V
CC
, but if more current is required, an external PNP transistor
can be added. When V
CC
is higher than V
BAT T
, the BAT T ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1
μ
F capacitor is connected to V
OUT
to
supply the transient currents for CMOS RAM. When V
CC
is
lower than V
BAT T
, an internal 20
MOSFET connects the
backup battery to V
OUT
.
R
=(
V
CC
– 50
mV
)/1
μ
A
Note that the resistor will discharge the battery slightly. With a
V
CC
supply of 4.5 V, a suitable resistor is 4.3 M
. With a 3 V
battery this will draw around 700 nA. T his will be negligible in
most cases.
ADM69x
V
BATT
BATTERY
R
Figure 22b. Preventing Spurious RESETS During Battery
Replacement
T Y PICAL APPLICAT IONS
ADM690, ADM692 AND ADM694
Figure 23 shows the ADM690/ADM692/ADM694 in a typical
power monitoring, battery backup application. V
OUT
powers the
CMOS RAM. Under normal operating conditions with V
CC
present, V
OUT
is internally connected to V
CC
. If a power failure
occurs, V
CC
will decay and V
OUT
will be switched to V
BAT T
thereby maintaining power for the CMOS RAM. A
RESET
pulse is also generated when V
CC
falls below 4.65 V for the
ADM690/ADM694 or 4.4 V for the ADM692.
RESET
will
remain low for 50 ms (200 ms for ADM694) after V
CC
returns
to 5 V.
T he watchdog timer input (WDI) monitors an I/O line from the
μ
P system. T his line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indi-
cates that the
μ
P system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
If the watchdog timer is not needed, the WDI input should be
left floating.
T he Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. T he voltage on the PFI input is com-
pared with a precision 1.3 V internal reference. If the input volt-
age drops below 1.3 V, a power fail output (
PFO
) signal is
generated. T his warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. T he resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage V
T
.
V
T
=
(1.3
R
1
/
R
2
)
+
1.3
V
R
1
/
R
2
= (
V
T
/1.3) – 1
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| ADM690AN | 功能描述:IC SUPERVISOR MPU 4.65 WD 8DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:高有效 復(fù)位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應(yīng)商設(shè)備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
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| ADM690ANZ | 制造商:Analog Devices 功能描述:Microprocessor Supervisor |
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