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參數(shù)資料
| 型號： | ADM4210-2AUJZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 278K |
| 描述： | IC CTLR HOTSWAP LV TSOT23-6 |
| 產(chǎn)品培訓(xùn)模塊： | Hot Swap Design |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 2.7 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 細型，TSOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | TSOT-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADM4210-2AUJZ-RL7DKR |
ADM4210
Data Sheet
Rev. A | Page 12 of 16
CIRCUIT BREAKER FUNCTION
When the supply experiences a sudden current surge, such as a
low impedance fault on load, the bus supply voltage can drop
significantly to a point where the power to an adjacent card is
affected, potentially causing system malfunctions. The
ADM4210 limits the current drawn by the fault by reducing the
gate voltage of the external FET. This minimizes the bus supply
voltage drop caused by the fault and protects neighboring cards.
As the voltage across the sense resistor approaches the current
limit, a timer activates. This timer resets again if the sense
voltage returns below this level. If the sense voltage is any
voltage below 44 mV, the timer is guaranteed to be off. Should
the current continue to increase, the ADM4210 tries to regulate
the gate of the FET to achieve a limit of 50 mV across the sense
resistor. However, if the device is unable to regulate the fault
current and the sense voltage further increases, a larger pull-
down, in the order of milliamperes, is enabled to compensate
for fast current surges. If the sense voltage is any voltage greater
than 56 mV, this pull-down is guaranteed to be on. When the
timer expires, the GATE pin shuts down.
TIMER FUNCTION
The TIMER pin is responsible for several key functions on the
ADM4210. A capacitor controls the initial power on reset time
and the amount of time an overcurrent condition lasts before
the FET shuts down. On the ADM4210-1, the timer pin also
controls the time between auto retry pulses. There are pull-up
and pull-down currents internally available to control the timer
functions. The voltage on the TIMER pin is compared with two
threshold voltages: COMP1 (0.2 V) and COMP2 (1.3 V). The
four timing currents are listed in Table 5.
Table 5.
Timing Current
Level (糀)
Pull-up
5
Pull-up
60
Pull-down
2
Pull-down
100
POWER-UP TIMING CYCLE
The ADM4210 is in reset when the ON (ON-CLR
) pin is held
low. The GATE pin is pulled low and the TIMER pin is pulled
low with a 100 糀 pull-down. At Time Point 2 in Figure 30, the
ON (ON-
CLR
) pin is pulled high. For the device to startup
correctly, the supply voltage must be above UVLO, the ON
(ON-
CLR
) pin must be above 1.3 V, and the TIMER pin voltage
must be less than 0.2 V. The initial timing cycle begins when these
three conditions are met, and the TIMER pin is pulled high with
5 糀. At Time Point 3, the TIMER reaches the COMP2 threshold.
This is the end of the first section of the initial cycle. The 100 糀
current source then pulls down the TIMER pin until it reaches
0.2 V at Time Point 4. The initial cycle delay (Time Point 2 to
Time Point 4) relates to CTIMER by equation
t
INITIAL
= 1.3 ?C
TIMER
/5 糀
(4)
When the initial cycle ends, a start-up cycle activates and the
GATE pin is pulled high; the TIMER pin continues to pull down.
1
2
NORMAL
CYCLE
INITIAL
CYCLE
START-UP
CYCLE
RESET
MODE
3
4
V
IN
V
ON
TIMER
V
GATE
V
OUT
Figure 30. Power-Up Timing
2礎(chǔ)
5礎(chǔ)
60礎(chǔ)
100礎(chǔ)
V
IN
V
ON
V
TIMER
V
GATE
V
OUT
I
RSENSE
NORMAL
CYCLE
INITIAL
CYCLE
START-UP
CYCLE
RESET
MODE
Figure 31. Power-Up into Capacitor
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