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| 型號： | ADM4210-2AUJZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 278K |
| 描述： | IC CTLR HOTSWAP LV TSOT23-6 |
| 產(chǎn)品培訓(xùn)模塊： | Hot Swap Design |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 2.7 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 細(xì)型，TSOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | TSOT-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADM4210-2AUJZ-RL7DKR |
Data Sheet
ADM4210
Rev. A | Page 11 of 16
THEORY OF OPERATION
Many systems require the insertion or removal of circuit boards
to live backplanes. During this event, the supply bypass and hold-
up capacitors can require substantial transient currents from the
backplane power supply as they charge. These currents can
cause permanent damage to connector pins or undesirable glitches
and resets to the system.
The ADM4210 is intended to control the powering of a system
(on and off) in a controlled manner, allowing the board to be
removed from, or inserted into, a live backplane by protecting it
from excess currents. The ADM4210 can reside either on the
backplane or on the removable board.
OVERVIEW
The ADM4210 operates over a supply range of 2.7 V to 16.5 V.
As the supply voltage is coming up, an undervoltage lockout
circuit checks if sufficient supply voltage is present for proper
operation. During this period, the FET is held off by the GATE
pin being held to GND. When the supply voltage reaches a level
above UVLO and the ON (ON-CLR
) pin is high, an initial timing
cycle ensures that the board is fully inserted in the backplane
before turning on the FET. The TIMER pin capacitor sets the
periods for all of the TIMER pin functions. After the initial
timing cycle, the ADM4210 monitors the inrush current
through an external sense resistor. Overcurrent conditions are
actively limited to 50 mV/RSENSE for the circuit breaker timer
limit. The ADM4210-1 automatically retries after a current
limit fault and the ADM4210-2 latches off. The retry duty cycle
on the ADM4210-1 timer function is limited to 3.8% for FET
cooling.
UVLO
If the VCC supply is too low for normal operation, an under-
voltage lockout circuit holds the ADM4210 in reset. The GATE
pin is held to GND during this period. When the supply reaches
this UVLO voltage, the ADM4210 starts when the ON (ON-
CLR
)
pin condition is satisfied.
ON (ON-CLR
) PIN
The ON (ON-
CLR
) pin is the enable pin. It is connected to a
comparator that has a low-to-high threshold of 1.3 V with 80 mV
hysteresis and a glitch filter. The ADM4210 is reset when the
ON (ON-CLR
) pin is low. When the ON (ON-CLR
) pin is high,
the ADM4210 is enabled. A rising edge on this pin has the
added function of clearing a fault and restarting the device on
the latched off model, the ADM4210-2. A low input on the ON
(ON-
CLR
) pin turns off the external FET by pulling the GATE
pin to ground and resets the timer. An external resistor divider at
the ON (ON-
CLR
) pin can be used to program an undervoltage
lockout value higher than the internal UVLO circuit. There is a
glitch filter delay of approximately 3 約 on rising allowing the
addition of an RC filter at the ON (ON-CLR
) pin to increase the
delay time at card insertion. If using a short pin system to
enable the device, a pull-down resistor should be used to hold
the device prior to insertion.
GATE
Gate drive for the external N-channel MOSFET is achieved
using an internal charge pump. The gate driver consists of a
12 糀 pull-up from the internal charge pump. There are various
pull-down devices on this pin. At a hot swap condition the board
is hot inserted to the supply bus. During this event, it is possible
for the external FET GATE capacitance to be charged up by the
sudden presence of the supply voltage. This can cause uncontrolled
inrush currents. An internal strong pull-down circuit holds
GATE low while in UVLO. This reduces current surges at inser-
tion. After the initial timing cycle, the GATE is then pulled high.
During an overcurrent condition, the ADM4210 servos the
GATE pin in an attempt to maintain a constant current to the
load until the circuit breaker timeout completes. In the event of
a timeout, the GATE pin abruptly shuts down using the 4 mA
pull-down device. Care must be taken not to load the GATE pin
resistively because this reduces the gate drive capability.
CURRENT LIMIT FUNCTION
The ADM4210 features a fast response current control loop that
actively limits the current by reducing the gate voltage of the
external FET. This current is measured by monitoring the
voltage drop across an external sense resistor. The ADM4210
tries to regulate the gate of the FET to achieve a 50 mV voltage
drop across the sense resistor.
CALCULATING THE CURRENT LIMIT
The sense resistor connected between V
CC
and the SENSE pin is
used to determine the nominal fault current limit. This is given
by the following equation:
ILIMITNOM = VCBNOM/RSENSENOM
(1)
The minimum load current is given by Equation 2
ILIMITMIN = VCBMIN/RSENSEMAX
(2)
The maximum load current is given by Equation 3
ILIMIT
MAX
= VCB
MAX
/RSENSE
MIN
(3)
For proper operation, the minimum current limit must exceed
the circuit maximum operating load current with margin. The
sense resistor power rating must exceed
(VCBMAX)
2
/RSENSEMIN
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