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參數(shù)資料
| 型號(hào)： | ADM1070ARTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大小： | 336K |
| 描述： | IC CTRLR HOTSWAP -48V SOT23-6 |
| 產(chǎn)品培訓(xùn)模塊： | Hot Swap Design |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開(kāi)關(guān)： | 無(wú) |
| 電源電壓： | -36 V ~ -77 V |
| 工作溫度： | -45°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 配用： | EVAL-ADM1073MEBZ-ND - BOARD EVALUATION FOR ADM1073 |
| 其它名稱(chēng)： | ADM1070ARTZ-REEL7DKR |
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REV. 0
12
ADM1070
FUNCTIONALITY AND TIMING
Live Insertion
The timing waveforms associated with the live insertion of a
plug-in board using the ADM1070 are shown in the following
figures. When the board connects the GND-V
EE
potential
climbs to 48 V. As this voltage is applied, the voltage at the V
IN
Pin ramps above the undervoltage lockout (V
LKO
) of 8.5 V to a
constant 12.3 V and is held at this level with the shunt resistor
and external resistor combination at the V
IN
Pin.
When UV/OV crosses the undervoltage rising threshold of
0.91 V, it is now inside the operating voltage window and the
48 V supply must be applied to the load. After a time delay,
t
POR
, the ADM1070 begins to ramp up the gate drive. When the
voltage on the SENSE Pin reaches 100 mV (the analog current
limit) the gate drive is held constant. When the board capaci-
tance is fully charged, the sense voltage begins to drop below
the analog current limit voltage and the gate voltage is free to
ramp up further. The gate voltage eventually reaches its maxi-
mum value of 12.3 V (as set by V
IN
).
GND-V
EE
t
POR
V
IN
UV/OV
GATE
SENSE
V
OUT
V
LKO
V
UVR
Figure 5. Timing Waveforms Associated with a
Live Insertion Event
GATE
SENSE
V
OUT
CH2
5.00V
CH1
10.00V
CH3
100mV M 500s CH1
2.8V
T
T
Figure 6. Start-Up Sequence
OVERVOLTAGE AND UNDERVOLTAGE
The waveforms for an overvoltage glitch are shown below.
When UV/OV glitches above the overvoltage rising threshold of
1.97 V, an overvoltage condition is detected and the gate volt-
age is pulled low. UV/OV begins to drop a back toward the
operating voltage window and the gate drive is restored when
the overvoltage falling threshold of 1.93 V is reached. Figure 7
illustrates the ADM1070s operation in an overvoltage situation.
GATE
SENSE
V
UV/OV
CH2
10.00V
CH1
1.00V
CH3
100mV M 200s CH3
1.96V
T
T
Figure 7. Timing Waveforms Associated with an
Overvoltage Glitch
An undervoltage glitch is dealt with in a similar way. When
V
UV/OV
falls below the undervoltage falling threshold of 0.86 V,
the gate voltage is pulled low. If UO/UV subsequently rises
back above the undervoltage rising threshold of 0.91 V, then the
gate voltage is restored. Figure 8 illustrates the ADM1070s
operation in an undervoltage situation.
GATE
SENSE
V
UV/OV
CH2
10.0V
CH1
1.00V
CH3
100mV M 200ms
Figure 8. Timing Waveforms Associated with an
Undervoltage Glitch
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| ADM1073ARU | 功能描述:IC CTRLR HOTSWAP -48V 14TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:119 系列:- 類(lèi)型:熱交換控制器 應(yīng)用:通用型，PCI Express? 內(nèi)部開(kāi)關(guān):無(wú) 電流限制:- 電源電壓:3.3V，12V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:80-TQFP 供應(yīng)商設(shè)備封裝:80-TQFP（12x12） 包裝:托盤(pán) 產(chǎn)品目錄頁(yè)面:1423 (CN2011-ZH PDF) |
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