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參數(shù)資料
| 型號(hào)： | ADM1060ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | CON-HDR64POS2ROW 4WALL.1X.1SP,RTANG,LOPF |
| 中文描述： | 7-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁數(shù)： | 31/45頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ADM1060ARU |
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ADM1060 STATUS/FAULTS
ADM1060
PRELIMINARY TECHNICAL DATA
–
31
–
REV. PrJ 11/02
F AUL T /ST AT US R E POR T ING ON T HE AD M1060
As discussed in the last section, any one, a number or all
of the PDO
’
s can be programmed to assert under a set of
pre- programmed conditons. T hese conditions could be a
fault on a SFD, a change in status on a GPI, a timeout on
the watchdog detector etc. Because of the flexibility and
the choice of combinations available on the ADM1060,
the assertion of the PDO will tell the user nothing about
what caused it to assert (unless it is programmed to assert
with only one input).
T o enable the user to debug the cause of the PDO asser-
tion, a number of registers are provided on the ADM1060
which provide status and fault information on the various
individual functions supervised by the device.
ST A T US R E GIST E R S
A number of Status Registers are provided which indicate
the logic state of all of the functions controlled by the
ADM1060. T hese logics states include the output of both
the UV and OV comparators of each of the 7 SFD
’
s, the
logic output of the SFD
’
s themselves, the logic state of
the GPI
’
s, the error condition on the WDI, and the logic
state of each of the 9 PDO
’
s. T he contents of these regis-
ters can be read at any time via the SMBus interface. T he
content of these registers is read- only. T he register and
bitmap for each of these status registers is described in the
table overleaf.
F A UL T R E GIST E R S
Fault reporting is also provided on the ADM1060. If a
fault occurs, causing, say, a PDO to change its status, the
user can determine what function actually faulted. T his is
achieved by providing a
“
fault plane
”
, consisting of 2
registers, LAT F1 and LAT F2, which the system control-
ler can read out of the ADM1060 via the SMBus. Each
bit in the 2 registers (with one important exception, see
below) is assigned to one of the inputs of the devices as
shown in the table below:-
R E GIST E R
BIT
ASSIGNE D FUNC T ION
L AT F1
7
ANY FL T
6
Logic Output of VP4
’
s SFD
5
Logic Output of VP3
’
s SFD
4
Logic Output of VP2
’
s SFD
3
Logic Output of VP1
’
s SFD
2
Logic Output of VH
’
s SFD
1
Logic Output of VB2
’
s SFD
0
Logic Output of VB1
’
s SFD
L AT F2
7
-
6
-
5
-
4
Logic Output of WDI
3
Logic Input on GPI4
2
Logic Input on GPI3
1
Logic Input on GPI2
0
Table 25. Fault Plane of ADM1060
Each bit represents the logical status of its assigned func-
tion (ie) the logical output of the SFD
’
s and WDI and the
logic level on the GPI inputs.
T he important exception is the MSB of the LAT F1 regis-
ter. T his is the ANYFLT bit. T his bit goes high if one
of the other bits in the 2 registers
“
faults
”
. A
“
fault
”
is
defined as a change in polarity from the last time the fault
registers were read. Once ANYFLT goes high the con-
tents of the 2 registers are latched, thus preventing more
than 1 of the other bits from changing polarity before the
contents of the registers are read. T he first faulting input
can, therefore, be determined.
T he sequence in which the registers are read is determined
by ANYFLT . As long as ANYFLT remains at 0, only the
contents of LAT F1 are read. T here are 2 reasons for this.
T he first is that ANYFLT =0 implies that no fault has
occurred and, therefore, there is no need to read the con-
tents of LAT F2. Secondly, and more importantly, read-
ing register LAT F2 actually resets the ANYFLT bit to 0.
T hus, if a fault occurred on an SFD after LAT F1 had
been read but before LAT F2 had been read, ANYFLT
would change to 1, indicating that a fault had occurred,
but would be reset to 0 once LAT F2 was read, thus eras-
ing the log of the fault. In summary then, LAT F2 should
only ever be read if ANYFLT =1. Reading the registers in
this sequence ensures that the contents are never reset
before a fault has been logged over the SMBus, thus en-
suring that the supervising processor or CPLD knows
what function supervised by the ADM1060 caused the
fault. T he
“
faulting
”
function is determined by compar-
ing the contents of the fault plane (ie) the contents of the 2
registers, with the values read previously, and determining
which bit changed polarity.
T he functionality of the Fault Plane is best illustrated with
an example. T ake, for instance, VP1 to have an input
supply of 5.0V. A UV/OV window of 4.5V to 5.5V is set
up on VP1. T he supply is ramped in and out of this win-
dow, each time reading the contents of LAT F1 and
LAT F2. T he values recorded are as follows:-
1. VP1 at 5V- LAT F1=LAT F2=00000000. T his is ex-
pected. T he supply is in tolerance, SFD output is 0,
therefore no fault.
2. VP1 at 4.2V- L AT F1=10001000, L AT F2=00000000.
SFD output has changed status to 1, therefore ANYFLT
goes high.
3. VP1 at 5.0V- L AT F1=10000000, L AT F2=00000000.
SFD output has changed status to 0, therefore ANYFLT
goes high again.
4. VP1 at 5.8V- L AT F1=10001000, L AT F2=00000000.
SFD output again changed status from 0 to 1, so
ANY FL T goes high.
5.VP1 at 4.2V- L AT F1=10000000, L AT F2=00000000.
At first glance, this would appear to be incorrect, since
SFD output should be at 1 (4.2V is an undervoltage
fault). However, in ramping down from 5.8V to 4.2V, the
supply passed into the UV/OV window, the SFD output
changed status from 1 to 0, ANYFLT was set high and
the register contents were latched. It is these values which
were read before being reset by reading LAT F2.
T here are also two mask registers provided, which enable
the user to ignore a fault on a given function. T he bits of
the error mask registers are mapped in the same way as
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