參數(shù)資料
型號: ADM1041ARQ-REEL
廠商: ANALOG DEVICES INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Secondary-Side Controller with Current Share and Housekeeping
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO24
封裝: MO-137AE, QSOP-24
文件頁數(shù): 47/64頁
文件大小: 1063K
代理商: ADM1041ARQ-REEL
ADM1041
Bit No.
3–2
1
0
Rev. A | Page 47 of 64
Name
ssrs1, ssrs0
add1
trim_lock
R/W
R/W
R/W
R/W
Description
0
1
1
Soft-Start Step
b3
0
0
1
1
EEPROM programmable second address bit.
When this bit is set, the trim registers including this register are not writable via SMBus. To
make registers writable again, the trim-lock bit in the EEPROM must first be erased and the
value downloaded using either power-up or test download.
1
0
1
2%
3%
4%
Rise Time
300 μs
10 ms
20 ms
40 ms
b2
0
1
0
1
Table 26. Register 11h, Config5. Power-On Default from EEPROM Register 8111h 8110h during Power-Up.
Bit No.
Name
R/W
Description
7
curr_lim_dis
R/W
Mask effect of OCP to general logic (status flag still gets asserted) when curr_lim_dis = 1.
6
polpen0
R/W
Sets polarity of PEN output. Refer to the Configuration table (Table 45).
5
polcbd0
R/W
Sets polarity of CBD output. Refer to the Configuration table (Table 45).
4–3
Reserved
X
Don’t Care.
2
ocpts2
R/W
Set this bit to 1 when 0 OCP ridethrough is required. A small delay still exists. Refer to Reg 12h
and the Configuration table (Table 45).
1
gndok_dis
R/W
Disable gndok input to power management debounce logic.
0
cbdlm
R/W
Select CBD latch mode. 0 = nonlatching; 1 = latching.
Table 27. Register 12h, Config6. Power-On Default from EEPROM Register 8112h 8110h during Power-Up.
Bit No.
Name
R/W
Description
7
rsm
R/W
Restart Mode. When rsm = 1, the circuit attempts to restart the supply after an undervoltage or
overcurrent at about 1 second intervals.
Latch Mode. When rsm = 0, UV and OC faults latch the output off. Cycling PSON or removing the
supply to the IC is then required to reset the latch and permit a restart.
6
up_AC_OK_m
R/W
Configure microprocessor to control/gate signal from acinok to acsok.
0 = standalone.
1 = microprocessor support mode.
5
m_acsns_w
(W)
Microcessor control of acsok (AC
SENSE
).
4–3
ocpts1, ocpts0
R/W
OCP Ridethrough (Reg 11h[2] = 0)
b4
b3
Period
0
0
1 second
0
1
2 seconds
1
0
3 seconds
1
1
4 seconds
2
acss
(W)
AC Sense Mode. 0 means AC_OK is derived from AC
SENSE
1, whereas 1 means AC_OK is derived from
AC
SENSE
2.
1
m_pson_w
(W)
Microprocessor control of pson.
0
I
SHARE
_clamp
R/W
0 = 75%. Set current share clamp release threshold.
1 = 88%.
OCP Ridethrough (Reg11h[2] = 1)
b4
b3
0
0
0
1
1
0
1
1
Period
128 μs
256 μs
384 μs
512 μs
Table 28. Register 13h, Config7. Power-On Default from EEPROM Register 8113h during Power-Up.
Bit No.
Name
R/W
Description
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