- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373995 > ADM1041ARQ-REEL (ANALOG DEVICES INC) Secondary-Side Controller with Current Share and Housekeeping PDF資料下載
參數(shù)資料
| 型號： | ADM1041ARQ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Secondary-Side Controller with Current Share and Housekeeping |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO24 |
| 封裝： | MO-137AE, QSOP-24 |
| 文件頁數(shù)： | 39/64頁 |
| 文件大?。?/td> | 1063K |
| 代理商： | ADM1041ARQ-REEL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
ADM1041
Notes on SMBus Read Operations
The SMBus interface of the ASIC cannot load the SMBUS if no
power is applied to the ASIC. This requirement allows a power
supply to be disconnected from the ac supply while still installed
in a power subsystem.
Rev. A | Page 39 of 64
When using the SMBus interface, a write always consists of the
ADM1041 SMBus interface address byte, followed by the
internal address register byte, and then the data byte. There are
two cases for a read:
If the internal address register is known to be at the desired
address, simply read the ASIC with the SMBus interface
address byte, followed by the data byte read from the ASIC.
The internal address pointer increments if a block mode
operation is in progress; data values of 0 are returned if the
register address limit of 7Fh is exceeded, or if unused
registers in the address range 00h to 7Fh are accessed. If
the address register is pointing at EEPROM memory, that
is 8000h, and the address reaches its limit of 80FFh, it does
not roll over to Address 8100h on the next access.
Additional accesses do not increment the address pointer,
all reads return 00h, and all writes complete normally but
do not change any internal register or EEPROM location. If
the address register is pointing at EEPROM memory, that
is 81xxh, and the address reaches its limit of 813Fh, it does
not roll over to Address 8140h on the next access.
Additional accesses do not increment the address pointer,
all reads return 00h, and all writes complete normally but
not change any internal register or EEPROM location. Note
that for byte reads, the internal address does not auto
increment.
If the internal address register value is unknown, write to
the ADM1041 with the SMBus interface address byte,
followed by the internal address register byte. Then restart
the serial communication with a read consisting of the
SMBus interface address byte, followed by the data byte
read from the ADM1041.
SMBus ALERT RESPONSE ADDRESS (ARA)
The ADM1041’s CBD/ALERT pin can be configured to respond
to a variety of fault signals and can be used as an interrupt to a
microprocessor. The pins from several ADM1041s may be wire-
ORed. When the SMBus master (microprocessor) detects an
alert request, it normally needs to read the alert status of each
device to identify the source of the alert.
The SMBus ARA provides an easier method to locate the source
of a such an alert. When the master receives an alert, it can send
a general call address (0001100) over the bus. The device assert-
ing the alert responds by returning its own slave address to the
master.
If more than one device is asserting an alert, all alerting devices
try to respond with their slave addresses, but an arbitration
process ensures that only the lowest slave address is received by
the master. If the slave device has its alert configured as latching,
it sends a command via the SMBus to clear the latch. The master
should then check if the alert line is still asserted, and, if so,
repeat the ARA call to service the next alert. Note that an alerting
slave does not respond to an ARA call unless it is configured in
SMBus mode (not AC_OKLink/PS
ON
LINK) and up_pson_m is
set. The ADM1041 supports the SMBus (ARA) function.
SUPPORT FOR SMBus 1.1
SMBus 1.1 optionally adds a CRC8 frame check sequence to
check if transmissions are received correctly. This is particularly
useful for long block read/write EEPROM operations, when the
SMBus is heavily loaded or in a noisy environment. The CRC8
frame can be used to guarantee reliability of the EEPROM.
LAYOUT CONSIDERATIONS
Noise coupling into the digital lines (greater than 150 mV),
overshoot greater than V
CC
and undershoot less than GND may
prevent successful SMBus communication with the ADM1041.
SMBus No Acknowledge is the most common symptom,
causing unnecessary traffic on the bus. Although the SMBus
maximum frequency of communication is rather low (400 kHz
max), care still needs to be taken to ensure proper termination
within a system with multiple parts on the bus and long printed
circuit board traces. A 5.1 k resistor can be added in series
with the SDA and SCL lines to help filter noise and ringing.
Minimize noise coupling by keeping digital traces out of
switching power supply areas and ensure that digital lines
containing high speed data communications cross at right
angles to the SDA and SCL lines.
POWER-UP AUTO-CONFIGURATION
After power-up or reset, the ADM1041 automatically reads the
content of a 32-byte block of EEPROM memory that starts at
8100h and transfers the contents into the appropriate trim-level
and control registers (00h to 1Bh). In this way, the ADM1041
can be preconfigured with the desired operating characteristics
without the host system having to download the data over the
SMBus. This does not preclude the possibility of modifying the
configuration during normal operation.
Figure 37 shows a block diagram of the EEPROM download at
power-up or power-on reset.
RAM
CONFIGURATION
REGISTERS
EEPROM
POWER UP
DIGITAL
TRIM
POTS
DIGITAL
TIMING
CONTROL
0
Figure 37. EEPROM Download
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADM1041ARQ-REEL7 | Secondary-Side Controller with Current Share and Housekeeping |
| ADM1041 | Secondary-Side Controller with Current Share and Housekeeping |
| ADM1041ARQ | Secondary-Side Controller with Current Share and Housekeeping |
| ADM1041A | Secondary-Side Controller with Current Share and Housekeeping |
| ADM1041AARQZ | Secondary-Side Controller with Current Share and Housekeeping |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADM1041ARQ-REEL7 | 功能描述:IC PWR SUP MON/LOAD SHARE 24QSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ADM1041ARQZ | 功能描述:IC PWR SUPP MON/LOAD SHAR 24QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ADM1041ARQZ-REEL | 功能描述:IC SECONDARY SIDE CTRLR 24QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ADM1041ARQZ-REEL7 | 功能描述:IC SECONDARY SIDE CTRLR 24QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ADM1041ARQZ-RL7 | 功能描述:IC SECONDARY SIDE CTRLR 24QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。