
ADM1041A
Pin No.
10
Rev. 0 | Page 15 of 56
Mnemonic
AC
SENSE
2/MON2
Description
AC/Bulk Sense Input 2 or Monitor 2 Input.
AC
SENSE
2: This alternative AC
SENSE
input can be used when the AC
SENSE
source must be different from that used
for the OrFET. It also allows dc and optocoupled signals that are not suitable for the OrFET control.
MON2: When MON2 is selected for this pin, its input is compared against a 1.25 V comparator that could be
used for monitoring a postregulated output; includes overvoltage, undervoltage, and overtemperature
conditions.
CBD: The crowbar drive pin allows implementation of a fast shutdown in case of a load overvoltage fault. The
pin can be configured as an open-drain N-channel or P-channel and is suitable for driving a sensitive gate SCR
crowbar. An external transistor is required if a high gate current is needed. Either polarity may be selected.
ALERT: This pin can be configured to provide an ALERT function in microprocessor-supported applications
where any of several ICs in a redundant system that detects a problem can interrupt and shut down the
power supply. An alternative use is as a general-purpose logic output signal.
Power Enable. This pin can be configured as an open-drain N-channel or P-channel that typically drives the
PEN optocoupler. Providing that the PSON pin has been asserted to turn the output on, and that there are no
faults, this pin drives an optocoupler on enabling the primary PWM circuit. Either polarity may be selected.
SCL: SMBus Serial Clock Input.
AC_OKLink: In nonmicroprocessor applications, this pin can be programmed to give the status of AC
SENSE
to all
the ICs on the same bus. The main effect is to turn on undervoltage blanking whenever the sense circuit
monitoring ac or bulk dc detects a low voltage.
SDA: SMBus Serial Data Input and Output.
PS
ON
LINK: In non-microprocessor applications, this pin can be programmed to provide the PSON status to
other ICs. This allows just one IC to be the PSON interface to the host system, or the PS
ON
LINK itself can be the
PSON interface.
Chip Address Pin. There are three addresses possible using this pin, which are achieved by tying ADD0 to
ground, tying to V
DD
, or being left to float. One address bit is available via programming at the
device/daughter card level, so the total number of addressable ICs can be increased to six.
PSON: In nonmicroprocessor configurations, this is power supply on. As a standard I/O, this pin is rugged
enough for direct interface with a customer’s system. Either polarity may be selected.
MON3: When MON3 is selected for this pin, its input is compared against a 1.25 V comparator that could be
used for monitoring a postregulated output; includes overvoltage, undervoltage, and overtemperature
conditions.
DC_OK: This pin is the output of a general-purpose digital I/O that can be configured as open-drain
N-channel or open-drain P-channel suitable for wire-OR'ing with other ICs and direct interfacing with a
customer’s system. Either polarity may be selected.
MON4: When MON4 is selected for this pin, its input is compared against a 1.25 V comparator that could be
used for overtemperature protection and for monitoring a postregulated output; includes overvoltage,
undervoltage, and overtemperature conditions.
Buffered Output, Overtemperature Protection, or Monitor 5.
AC_OK: This option can be configured as N-channel or P-channel and as normal or inverted polarity. At
system level, a true AC_OK is used to indicate that the primary bulk voltage is high enough to support the
system and, when false, that dc output is about to fail.
MON5: A further option is to configure this as an analog input, MON5, with a flexible hysteresis and
trimmable 2.5 V reference. This makes the pin particularly suitable for overtemperature protection (OTP)
sensing. Since hysteresis uses a switched 100 μA current source, hysteresis can be adjusted via the source
impedance of the external circuit. It can also be used for OVP and UVP functions.
FET Gate Enable. When supporting an OrFET circuit, this is the gate drive pin. Because the open-drain voltage
on the chip is limited to V
DD
, an external level shifter is required to drive the higher gate voltages suitable for
the OrFET. This pin is configured as an open-drain N-channel. Either output polarity, low = on or low = off,
may be selected.
This pin is used as the ground input reference for the current share and load voltage sense circuits. It should
be tied to ground at the common remote sense location. The input impedance is about 35 kΩ to ground.
This pin is the positive remote load voltage sense input and is normally divided down from the power supply
output voltage to 2.0 V at no-load using an external voltage divider. The input impedance is high.
Output of the Current Share Transconductance Error Amplifier. Compensation is a series capacitor and
resistor to ground. While V
DD
is normal and PEN is false, this pin is clamped to ground. When the converter is
enabled (PEN true) and the clamp is released, the compensation capacitor charges, providing a slow walk-in.
The error amplifier input has a built-in bias so that all slaves in a parallel supply system do not compete with
the master for control of the share bus.
11
CBD/ALERT
12
PEN
13
SCL/AC_OKLink
14
SDA/PS
ON
LINK
15
ADD0
16
PSON/MON3
17
DC_OK/MON4
18
AC_OK/OTP/
MON5
19
F
G
20
V
S
–/SHRS–
21
V
S
+
22
SCMP