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參數(shù)資料
| 型號： | ADM1041AARQZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Secondary-Side Controller with Current Share and Housekeeping |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO24 |
| 封裝： | LEAD FREE, MO-137AE, QSOP-24 |
| 文件頁數(shù)： | 48/56頁 |
| 文件大小： | 991K |
| 代理商： | ADM1041AARQZ-REEL7 |
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ADM1041A
Table 40. Register 2Bh, Status2 Mirror Latched. Power-On Default 00h.
These flags are cleared by a register read, provided the fault no longer persists. See also Table 43. Note that latched bits are clocked on a
low-to-high transmission only. Also note that these register bits are cleared when read via the SMBus, except if the fault is still present. It
is recommended to read the register again after faults disappear to ensure reset.
Rev. 0 | Page 48 of 56
Bit No.
7
6
5
4
3
2
1
0
Name
Share_OK Latch
OrFET OK Latch
Reverse OK Latch
V
DD
OK Latch
GND OK Latch
intrefok Latch
extrefok Latch
V
DD
OV Latch
R/W
R
R
R
R
R
R
R
R
Description
Share_OK fault
ORFET fault
Reverse_OK fault
V
DD
OK fault
GND_OK fault
Internal reference fault
External reference fault
V
DD
OK fault
Table 41. Register 2Ch, Status3 Mirror Latched. Power-On Default 00h
These flags are cleared by a register read, provided the fault no longer persists. See also Table 43. Note that latched bits are clocked on a
low-to-high transmission only. Also note that these register bits are cleared when read via the SMBus, except if the fault is still present. It
is recommended to read the register again after the faults disappear to ensure reset.
Bit No.
7
6
5
4
3
2
1
0
MANUFACTURING DATA
Table 42.
Register
Register 81F0h
Register 81F1h
Register 81F2h
Register 81F3h
Register 81F4h
Register 81F5h
Register 81F6h
Register 81F7h
Register 81F8h
Register 81F9h
Register 81FAh
Register 81FBh
Register 81FCh
Register 81FDh
Register 81FEh
Register 81FFh
Name
m_acsns_r Latch
m_pson_r Latch
m_penok_r Latch
m_psonok_r Latch
m_DC_OK_r Latch
OCP Latch
PULSE_OK Latch
Fault
R/W
R
R
R
R
R
R
R
R
Description
AC_OK fault
PSON fault
PEN fault
PS
ON
LINK fault
DC_OK fault
OCP fault
Pulse fault
Fault latch
Description
PROBE1_BIN
PROBE2_BIN
F T _ B I N
PROBE1_CHKSUM
PROBE2_CHKSUM
FT_CHKSUM
QUAL_PART_ID
Probe 1 cell current data (integer)
Probe 1 cell current data (two decimal places)
Probe 2 cell current data (integer)
Probe 2 cell current data (two decimal places)
Final test cell current data (integer)
Final test cell current data (two decimal places)
Probe X coordinate
Probe Y coordinate
Wafer number
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADM1041A-EVALZ | 功能描述:BOARD EVAL FOR ADM1041A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - DC/DC 與 AC/DC（離線）SMPS 系列:- 標準包裝:1 系列:- 主要目的:DC/DC，步降 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:3.3V 電流 - 輸出:3A 輸入電壓:4.5 V ~ 28 V 穩(wěn)壓器拓撲結構:降壓 頻率 - 開關:250kHz 板類型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名稱:497-12113STEVAL-ISA094V1-ND |
| ADM1041ARQ | 功能描述:IC PWR SUPP MON/LOAD SHAR 24QSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ADM1041ARQ-2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADM1041ARQ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Secondary-Side Controller with Current Share and Housekeeping |
| ADM1041ARQ-REEL7 | 功能描述:IC PWR SUP MON/LOAD SHARE 24QSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
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