參數(shù)資料
型號(hào): ADM1041A
廠商: Analog Devices, Inc.
英文描述: Secondary-Side Controller with Current Share and Housekeeping
中文描述: 二次側(cè)電流控制器共享和管家
文件頁(yè)數(shù): 36/56頁(yè)
文件大小: 991K
代理商: ADM1041A
ADM1041A
Notes on SMBus Read Operations
The SMBus interface of the ADM1041A cannot load the
SMBUS if no power is applied to the ADM1041A. This
requirement allows a power supply to be disconnected from the
ac supply while still installed in a power subsystem.
Rev. 0 | Page 36 of 56
When using the SMBus interface, a write always consists of the
ADM1041A SMBus interface address byte, followed by the
internal address register byte, and then the data byte. There are
two cases for a read.
In the first case, if the internal address register is known to be at
the desired address, read the ADM1041A with the SMBus
interface address byte, followed by the data byte read from the
ADM1041A. The internal address pointer increments if a block
mode operation is in progress; data values of 0 are returned if
the register address limit of 7Fh is exceeded or if unused
registers in the address range 00h to 7Fh are accessed. If the
address register is pointing at EEPROM memory, that is 8000h,
and the address reaches its limit of 80FFh, it does not roll over
to Address 8100h on the next access.
Additional accesses do not increment the address pointer, all
reads return 00h, and all writes complete normally but do not
change any internal register or EEPROM location. If the address
register is pointing at EEPROM memory, that is 81xxh, and the
address reaches its limit of 813Fh, it does not roll over to
Address 8140h on the next access.
Additional accesses do not increment the address pointer, all
reads return 00h, and all writes complete normally but do not
change any internal register or EEPROM location. Note that for
byte reads, the internal address does not auto-increment.
In the second case, if the internal address register value is
unknown, write to the ADM1041A with the SMBus interface
address byte, followed by the internal address register byte.
Then restart the serial communication with a read consisting of
the SMBus interface address byte, followed by the data byte read
from the ADM1041A.
SMBus ALERT RESPONSE ADDRESS (ARA)
The ADM1041A CBD/ALERT pin can be configured to
respond to a variety of fault signals and can be used as an
interrupt to a microprocessor. The pins from several
ADM1041As may be wire-OR’ed. When the SMBus master
(microprocessor) detects an alert request, it normally needs to
read the alert status of each device to identify the source of the
alert.
The SMBus ARA provides an easier method to locate the source
of a such an alert. When the master receives an alert, it can send
a general call address (0001100) over the bus. The device assert-
ing the alert responds by returning its own slave address to the
master.
If more than one device asserts an alert, all alerting devices try
to respond with their slave addresses, but an arbitration process
ensures that only the lowest slave address is received by the
master. If the slave device has its alert configured as latching, it
sends a command via the SMBus to clear the latch. The master
should then check if the alert line is still asserted, and, if so,
repeat the ARA call to service the next alert. Note that an
alerting slave does not respond to an ARA call unless it is
configured in SMBus mode (not AC_OKLink/PS
ON
LINK) and
up_pson_m is set. The ADM1041A supports the SMBus (ARA)
function.
SUPPORT FOR SMBus 1.1
SMBus 1.1 optionally adds a CRC8 frame check sequence to
check if transmissions are received correctly. This is particularly
useful for long block read/write EEPROM operations, when the
SMBus is heavily loaded or in a noisy environment. The CRC8
frame can be used to guarantee reliability of the EEPROM.
LAYOUT CONSIDERATIONS
Noise coupling into the digital lines (greater than 150 mV),
overshoot greater than V
CC,
and undershoot less than GND
may prevent successful SMBus communication with the
ADM1041A. SMBus No Acknowledge is the most common
symptom, causing unnecessary traffic on the bus. Although the
SMBus maximum frequency of communication is rather low
(400 kHz max), care still needs to be taken to ensure proper
termination within a system with multiple parts on the bus and
long printed circuit board traces. A 5.1 kΩ resistor can be added
in series with the SDA and SCL lines to help filter noise and
ringing. Minimize noise coupling by keeping digital traces out
of switching power supply areas and ensure that digital lines
containing high speed data communications cross at right
angles to the SDA and SCL lines.
POWER-UP AUTO-CONFIGURATION
After power-up or reset, the ADM1041A automatically reads
the content of a 32-byte block of EEPROM memory that starts
at 8100h and transfers the contents into the appropriate trim-
level and control registers (00h to 1Bh). In this way, the
ADM1041A can be preconfigured with the desired operating
characteristics without the host system having to download the
data over the SMBus. This does not preclude the possibility of
modifying the configuration during normal operation.
Figure 37 shows a block diagram of the EEPROM download at
power-up or power-on reset.
RAM
CONFIGURATION
REGISTERS
EEPROM
POWER UP
DIGITAL
TRIM
POTS
DIGITAL
TIMING
CONTROL
0
Figure 37. EEPROM Download
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