參數(shù)資料
型號(hào): ADM1031ARQZ-REEL
廠商: ANALOG DEVICES INC
元件分類(lèi): 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 3Cel, RECTANGULAR, SURFACE MOUNT
封裝: LEAD FREE, MO-137AB, QSOP-16
文件頁(yè)數(shù): 14/36頁(yè)
文件大?。?/td> 596K
代理商: ADM1031ARQZ-REEL
ADM1031
Rev. B | Page 21 of 36
Figure 34 shows the behavior of the PWM output as
temperature varies. As the temperature rises, the fan speed
ramps up. Small drops in temperature do not affect the ramp-up
function because the newly calculated fan speed is still higher
than the previous PWM value. The filtered mode allows the
PWM output to be made less sensitive to temperature
variations. This is dependent on the ramp rate selected and the
ADC sample rate programmed into the fan filter register.
90
PWM DUTY CYCLE
0
TIME (s)
P
W
M
DUTY
CY
CLE
(%)
80
70
60
30
40
50
10
20
90
0
R
TEM
P
(
°C)
80
70
60
40
50
30
10
20
RTEMP
02402-034
Figure 34. How Fan Reacts to Temperature Variation in Filtered Mode
Effect of ADC Sample Rate on Filtered Mode
The second way to change the filtered mode characteristics is to
adjust the ADC sample rate. The faster the ADC sample rate,
the more temperature samples are obtained per second. One
way to apply filtering to the control loop is to slow down the
ADC sampling rate. This means that the number of iterations of
the filtered mode algorithm per second is effectively reduced. If
the number of temperature measurements per second is
reduced, how often the PWM_OUT signal controlling the fan is
updated is also reduced.
Bits <4:2> of the fan filter register (Register 0×23) set the ADC
sample rate. The default ADC sample rate is 1.4 kHz. The ADC
sample rate is selectable from 87.5 Hz to 11.2 kHz. Table 13
shows how many temperature samples are obtained per second,
for each of the ADC sample rates.
Table 13. Temperature Updates per Second
ADC Sample Rate
Temperature Updates/Sec
87.5 Hz
0.0625
175 Hz
0.125
350 Hz
0.25
700 kHz
0.5
1.4 kHz
1 (Default)
2.8 kHz
2
5.6 kHz
4
11.2 kHz
8
Relevant Registers for Filtered Automatic Fan Speed
Control Mode
In addition to the registers used to program the normal
automatic fan speed control mode, the following register needs
to be programmed.
Register 0×23 Fan Filter Register
<7> Spin-up Disable: When this bit is set to 1, fan spin-up is
disabled. (Default = 0)
<6:5> Ramp Rate: These bits set the ramp rate for filtered mode.
00 = 1 (0.416% Duty Cycle Change)
01 = 2 (0.833% Duty Cycle Change)
10 = 4 (1.66% Duty Cycle Change)
11 = 8 (3.33% Duty Cycle Change)
<4:2> ADC Sample Rate.
000 = 87.5 Hz
001 = 175 Hz
010 = 350 Hz
011 = 700 Hz
100 = 1.4 kHz (Default)
101 = 2.8 kHz
110 = 5.6 kHz
111 = 11.2 kHz
<1> Fan 2 Filter Enable: When this bit is set to 1, it enables
filtering on Fan 2. Default = 0.
<0> Fan 1 Filter Enable: When this bit is set to 1, it enables
filtering on Fan 1. Default = 0.
Programming the Filtered Automatic Fan Speed Control
Loop
1.
Program a value for TMIN.
2.
Program a value for the slope TRANGE.
3.
TMAX = TMIN + TRANGE.
4.
Program a value for fan spin-up time.
5.
Program the desired automatic fan speed control mode
behavior, that is, which temperature channel controls the
fan.
6.
Program a ramp rate for the filtered mode.
7.
Program the ADC sample rate in the fan filter register.
8.
Set Bit 0 to enable fan filtered mode for Fan 1.
9.
Set Bit 1 to enable the fan filtered mode for Fan 2.
10. Select automatic fan speed control mode by setting Bit 7 of
Configuration Register 1.
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