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| 型號： | ADM1026 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete Thermal and System Management Controller |
| 中文描述： | 完整的熱和系統(tǒng)管理控制器 |
| 文件頁數(shù)： | 47/56頁 |
| 文件大小： | 634K |
| 代理商： | ADM1026 |
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ADM1026
Rev. A | Page 47 of 56
Table 50. Register 25h, Status Register 6 (Power-On Default 00h)
Bit Name
R/W
1
Description
When GPIO8 is configured as an input, this bit is set when GPIO8 is asserted. (Asserted may be active
high or active low depending on setting of Bit 1 in GPIO Configuration Register 3.)
When GPIO8 is configured as an output, setting this bit asserts GPIO8. (Asserted may be active high or
active low depending on setting of Bit 1 in GPIO Configuration Register 3.)
When GPIO9 is configured as an input, this bit is set when GPIO9 is asserted. (Asserted may be active
high or active low depending on setting of Bit 3 in GPIO Configuration Register 3.)
When GPIO9 is configured as an output, setting this bit asserts GPIO9. (Asserted may be active high or
active low depending on setting of Bit 3 in GPIO Configuration Register 3.)
When GPIO10 is configured as an input, this bit is set when GPIO10 is asserted. (Asserted may be
active high or active low depending on setting of Bit 5 in GPIO Configuration Register 3.)
When GPIO10 is configured as an output, setting this bit asserts GPIO10. (Asserted may be active high
or active low depending on setting of Bit 5 in GPIO Configuration Register 3.)
When GPIO11 is configured as an input, this bit is set when GPIO11 is asserted. (Asserted may be
active high or active low depending on setting of Bit 7 in GPIO Configuration Register 3.)
When GPIO11 is configured as an output, setting this bit asserts GPIO11. (Asserted may be active high
or active low depending on setting of Bit 7 in GPIO Configuration Register 3.)
When GPIO12 is configured as an input, this bit is set when GPIO12 is asserted. (Asserted may be
active high or active low depending on setting of Bit 1 in GPIO Configuration Register 4.)
When GPIO12 is configured as an output, setting this bit asserts GPIO12. (Asserted may be active high
or active low depending on setting of Bit 1 in GPIO Configuration Register 4.)
When GPIO13 is configured as an input , this bit is set when GPIO13 is asserted. (Asserted may be
active high or active low depending on setting of Bit 3 in GPIO Configuration Register 4.)
When GPIO13 is configured as an output, setting this bit asserts GPIO13. (Asserted may be active high
or active low depending on setting of Bit 3 in GPIO Configuration Register 4.)
When GPIO14 is configured as an input , this bit is set when GPIO14 is asserted. (Asserted may be
active high or active low depending on setting of Bit 5 in GPIO Configuration Register 4.)
When GPIO14 is configured as an output, setting this bit asserts GPIO14. (Asserted may be active high
or active low depending on setting of Bit 5 in GPIO Configuration Register 4.)
When GPIO15 is configured as an input, this bit is set when GPIO15 is asserted. (Asserted may be
active high or active low depending on setting of Bit 7 in GPIO Configuration Register 4.)
When GPIO15 is configured as an output, setting this bit asserts GPIO15. (Asserted may be active high
or active low depending on setting of Bit 7 in GPIO Configuration Register 4.)
0
GPIO8 Status = 0
R
R/W
1
GPIO9 Status = 0
R
R/W
2
GPIO10 Status = 0
R
R/W
3
GPIO11 Status = 0
R
R/W
4
GPIO12 Status = 0
R
R/W
5
GPIO13 Status = 0
R
R/W
6
GPIO14 Status = 0
R
R/W
7
GPIO15 Status = 0
R
R/W
1
GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.
Table 51. Register 26h, V
BAT
Measured Value (Power-On Default 00h)
Bit
Name
7–0
V
BAT
Value
R/W
R
Description
This register contains the measured value of the V
BAT
analog input channel.
Table 52. Register 27h, A
IN8
Measured Value (Power-On Default 00h)
Bit
Name
7–0
A
IN8
Value
R/W
R
Description
This register contains the measured value of the A
IN8
analog input channel.
Table 53. Register 28h, EXT1 Measured Value (Power-On Default 00h)
Bit
Name
7–0
Ext1 Value
R/W
R
Description
This register contains the measured value of the Ext1 Temp channel.
Table 54. Register 29h, EXT2/A
IN9
Measured Value (Power-On Default 00h)
Bit
Name
R/W
7–0
Ext2 Temp/ A
IN9
Low Limit
R
Description
This register contains the measured value of the Ext2 Temp/A
IN9
channel depending on
which bit is configured.
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