參數(shù)資料
型號： ADG791ABCPZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 2/24頁
文件大?。?/td> 0K
描述： IC MUX/DEMUX QUAD 2X1 24LFCSP
產品變化通告： ADG79xx Discontinuance Notice 17/Aug/2010
標準包裝： 1
功能： 多路復用器/多路分解器
電路： 4 x 2:1
導通狀態(tài)電阻： 4 歐姆
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3V，5V
電流 - 電源： 1nA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤，CSP
供應商設備封裝： 24-LFCSP-VQ（4x4）
包裝： 標準包裝
其它名稱： ADG791ABCPZ-REELDKR
ADG791A/ADG791G
Rev. 0 | Page 10 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
S1A
2
S1B
3
D1
4
D2
5
S2B
6
S2A
15 NC
16 NC
17 NC
18 A2
14 NC
13 NC
7
S
3A
8
S
3B
9
D
3
11
S
4B
12
S
4A
10
D
4
21
S
C
L
22
S
D
A
23
V
D
24
G
N
D
20
A
0
19
A
1
ADG791A
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE TIED TO GND.
06
03
3-
0
04
PIN 1
INDICATOR
1
S1A
2
S1B
3
D1
4
D2
5
S2B
6
S2A
15 NC
16 GPO1
17 NC
18 A2
14 NC
13 NC
7
S
3A
8
S
3B
9
D
3
11
S
4B
12
S
4A
10
D
4
21
S
C
L
22
S
D
A
23
V
D
24
G
N
D
20
A
0
19
A
1
ADG791G
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE TIED TO GND.
06
03
3-
0
03
Figure 3. ADG791G Pin Configuration
Figure 4. ADG791A Pin Configuration
Table 5. ADG791A/ADG791G Pin Function Descriptions
Pin No.
Mnemonic
Description
1
S1A
A-Side Source Terminal for Mux 1. Can be an input or output.
2
S1B
B-Side Source Terminal for Mux 1. Can be an input or output.
3
D1
Drain Terminal for Mux 1. Can be an input or output.
4
D2
Drain Terminal for Mux 2. Can be an input or output.
5
S2B
B-Side Source Terminal for Mux 2. Can be an input or output.
6
S2A
A-Side Source Terminal for Mux 2. Can be an input or output.
7
S3A
A-Side Source Terminal for Mux 3. Can be an input or output.
8
S3B
B-Side Source Terminal for Mux 3. Can be an input or output.
9
D3
Drain Terminal for Mux 3. Can be an input or output.
10
D4
Drain Terminal for Mux 4. Can be an input or output.
11
S4B
B-Side Source Terminal for Mux 4. Can be an input or output.
12
S4A
A-Side Source Terminal for Mux 4. Can be an input or output.
13
NC
Not Internally Connected.
14
NC
Not Internally Connected.
15
NC
Not Internally Connected.
16
NC/GPO1
Not Internally Connected for ADG791A/General-Purpose Logic Output 1 for ADG791G.
17
NC
Not Internally Connected.
18
A2
Logic Input. Sets Bit A2 from the least significant bit of the 7-bit slave address.
19
A1
Logic Input. Sets Bit A1 from the least significant bit of the 7-bit slave address.
20
A0
Logic Input. Sets Bit A0 from the least significant bit of the 7-bit slave address.
21
SCL
Digital Input, Serial Clock Line. Open-drain input that is used in conjunction with SDA to clock data into
the device. External pull-up resistor required.
22
SDA
Digital I/O. Bidirectional, open-drain data line. External pull-up resistor required.
23
VDD
Positive Power Supply Input.
24
GND
Ground (0 V) Reference.
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