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參數(shù)資料
| 型號(hào)： | ADG3300BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XLATOR 8CH 1.2/5.5V 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 邏輯功能： | 變換器，雙向 |
| 位數(shù)： | 8 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 數(shù)據(jù)速率： | 50Mbps |
| 通道數(shù)： | 8 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 6ns |
| 電源電壓： | 1.15 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 802 (CN2011-ZH PDF) |
| 其它名稱： | ADG3300BRUZ-REEL7DKR |
ADG3300
Rev. 0 | Page 17 of 20
APPLICATIONS
The ADG3300 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pins, and the higher voltage logic signals are connected to the
Y pins. The ADG3300 can provide level translation in both
directions from A Y and Y A on all eight channels, eliminating
the need for a level translator IC for each direction. The internal
architecture allows the ADG3300 to perform bidirectional level
translation without an additional signal to set the direction of
the translation. It also allows simultaneous data flow in both
directions on the same part, for example, four channels translate
in the A Y direction while the other four translate in the Y A
direction. This simplifies the design by eliminating the timing
requirements for the direction signal and reduces the number of
ICs used for level translation.
Figure 36 shows an application where a 1.8 V microprocessor
can read or write data to or from a 3.3 V peripheral device using
an 8-bit bus.
VCCY
Y1
Y2
Y3
Y4
EN
GND
A4
A3
A2
A1
VCCA
MICROPROCESSOR/
MICROCONTROLLER/
DSP
1.8V
3.3V
PERIPHERAL
DEVICE
100nF
I/OL1
I/OL4
I/OL3
I/OL2
I/OH1
I/OH4
I/OH3
I/OH2
GND
05061-
038
GND
Y5
Y6
Y7
Y8
A8
A7
A6
A5
ADG3300
I/OL5
I/OL8
I/OL7
I/OL6
I/OH5
I/OH8
I/OH7
I/OH6
Figure 36. 1.8 V to 3.3 V 8-Bit Level Translation Circuit
When the application requires level translation between a
microprocessor and multiple peripheral devices, the ADG3300
Y I/O pins (Y1 to Y8) can be three-stated by setting EN = 0.
This feature allows the ADG3300 to share the data buses with
other devices without causing contention issues. Figure 37 shows
an application where a 3.3 V microprocessor is connected to
1.8 V peripheral devices using the three-state feature.
05061-039
Y1
VCCY
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
GND
A8
A7
A6
A5
A4
A3
A2
A1
VCCA
ADG3300
MICROPROCESSOR/
MICROCONTROLLER/
DSP
I/OH1
CS
3.3V
1.8V
PERIPHERAL
DEVICE 1
100nF
I/OH2
I/OH8
I/OH7
I/OH6
I/OH5
I/OH4
I/OH3
I/OL1
I/OL2
I/OL8
I/OL7
I/OL6
I/OL5
I/OL4
I/OL3
GND
1.8V
100nF
I/OL1
I/OL2
I/OL8
I/OL7
I/OL6
I/OL5
I/OL4
I/OL3
GND
PERIPHERAL
DEVICE 2
VCCY
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
GND
A8
A7
A6
A5
A4
A3
A2
A1
ADG3300
VCCA
Figure 37. 1.8 V to 3.3 V Level Translation Circuit
Using the Three-State Feature
LAYOUT GUIDELINES
As with any high speed digital IC, the printed circuit board
layout is important in the overall circuit performance. Care
should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each VCC pin (VCCA and
VCCY) should be bypassed using low effective series resistance
(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the VCCA and VCCY pins. The parasitic induc-
tance of the high speed signal track might cause significant
overshoot. This effect can be reduced by keeping the length
of the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.
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