I CCY (mA) 13 23 33 43 53 63 73 CAPACITIVE LOAD (pF) " />
參數(shù)資料
型號(hào): ADG3300BRUZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 20/20頁(yè)
文件大?。?/td> 0K
描述: IC XLATOR 8CH 1.2/5.5V 20-TSSOP
標(biāo)準(zhǔn)包裝: 1
邏輯功能: 變換器,雙向
位數(shù): 8
輸入類(lèi)型: 邏輯
輸出類(lèi)型: 邏輯
數(shù)據(jù)速率: 50Mbps
通道數(shù): 8
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無(wú)/無(wú)
傳輸延遲(最大): 6ns
電源電壓: 1.15 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 802 (CN2011-ZH PDF)
其它名稱(chēng): ADG3300BRUZ-REEL7DKR
ADG3300
Rev. 0 | Page 9 of 20
0
1
2
3
4
5
6
7
8
9
I CCY
(mA)
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
05061-009
TA = 25°C
1 CHANNEL
VCCA = 1.8V
VCCY = 3.3V
30Mbps
20Mbps
10Mbps
5Mbps
50Mbps
Figure 9. ICCY vs. Capacitive Load at Pin Y for A Y (1.8 V 3.3 V)
Level Translation
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
I CCA
(mA)
13
23
33
43
53
CAPACITIVE LOAD (pF)
05061-010
50Mbps
TA = 25°C
1 CHANNEL
VCCA = 1.8V
VCCY = 3.3V
5Mbps
10Mbps
20Mbps
30Mbps
Figure 10. ICCA vs. Capacitive Load at Pin A for Y A (3.3 V 1.8 V)
Level Translation
0
2
4
6
8
10
12
I CCY
(mA)
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
05061-011
TA = 25°C
1 CHANNEL
VCCA = 3.3V
VCCY = 5V
50Mbps
30Mbps
20Mbps
10Mbps
5Mbps
Figure 11. ICCY vs. Capacitive Load at Pin Y for A Y (3.3 V 5 V)
Level Translation
0
2
4
6
I CCA
(mA)
13
23
33
43
53
CAPACITIVE LOAD (pF)
05061-012
TA = 25°C
1 CHANNEL
VCCA = 3.3V
VCCY = 5V
50Mbps
30Mbps
20Mbps
10Mbps
5Mbps
1
3
5
7
Figure 12. ICCA vs. Capacitive Load at Pin A for Y A (5 V 3.3 V)
Level Translation
0
1
2
3
4
5
6
7
8
9
10
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
R
ISE
TIM
E
(n
s)
TA = 25°C
1 CHANNEL
DATA RATE = 50kbps
VCCA = 1.2V, VCCY = 1.8V
VCCA = 1.8V, VCCY = 3.3V
VCCA = 3.3V, VCCY = 5V
05061-013
Figure 13. Rise Time vs. Capacitive Load at Pin Y (A Y Level Translation)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
FALL
TIME
(ns)
TA = 25°C
1 CHANNEL
DATA RATE = 50kbps
VCCA = 1.8V, VCCY = 3.3V
VCCA = 3.3V, VCCY = 5V
VCCA = 1.2V, VCCY = 1.8V
05061-014
Figure 14. Fall Time vs. Capacitive Load at Pin Y (A Y Level Translation)
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