參數(shù)資料
型號(hào)： ADF4212LBRUZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/28頁(yè)
文件大?。?/td> 0K
描述： IC PLL FREQ SYNTHESIZER 20TSSOP
標(biāo)準(zhǔn)包裝： 2,500
類型： 時(shí)鐘/頻率合成器（RF/IF）
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 3:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無(wú)
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
ADF4212L
Data Sheet
Rev. E | Page 14 of 28
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 29 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no dead zone in the PFD transfer function and
gives a consistent reference spur level.
D1
Q1
CLR1
U1
U3
DELAY
HI
UP
D2
Q2
CLR2
U2
DOWN
+IN
HI
–IN
CHARGE
PUMP
CP
02
77
4-
0
29
Figure 29. RF/IF PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4212L allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by P3, P4, P11, and P12 (see Table 8 and Table 10).
Figure 30 shows the MUXOUT section in block diagram form.
LOCK DETECT
MUXOUT can be programmed for two types of lock detect: digital
lock detect and analog lock detect. Digital lock detect is active
high. It is set high when the phase error on three consecutive phase
detector cycles is less than 15 ns. It stays set high until a phase
error of greater than 25 ns is detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be operated
with an external pull-up resistor of 10 kΩ nominal. When lock
has been detected, it is high with narrow, low-going pulses.
IF ANALOG LOCK DETECT
IF R COUNTER OUTPUT
IF N COUNTER OUTPUT
IF/RF ANALOG LOCK DETECT
RF R COUNTER OUTPUT
RF N COUNTER OUTPUT
RF ANALOG LOCK DETECT
MUX
CONTROL
MUXOUT
DVDD
DGND
0
2774-
03
0
Figure 30. MUXOUT Schematic
RF/IF INPUT SHIFT REGISTER
The ADF4212L digital section includes a 24-bit input shift
register, a 15-bit IF R counter, and an 18-bit IF N counter
(comprising a 6-bit IF A counter and a 12-bit IF B counter).
Also present is a 15-bit RF R counter and an 18-bit RF N
counter (comprising a 6-bit RF A counter and a 12-bit RF B
counter). Data is clocked into the 24-bit shift register on each
rising edge of CLK. The data is clocked in MSB first. Data is
transferred from the shift register to one of four latches on the
rising edge of LE. The destination latch is determined by the
state of the two control bits (C2, C1) in the shift register. These
are the two LSBs, DB1 and DB0, as shown in the timing diagram
of Figure 2. The truth table for these bits is shown in Table 6.
Table 7 shows a summary of how the latches are programmed.
Table 6. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
0
IF R counter
0
1
IF N counter (A and B)
1
0
RF R counter
1
RF N counter (A and B)
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