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參數(shù)資料
型號: ADF4112BRUZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 22/28頁
文件大小: 0K
描述: IC PLL RF FREQ SYNTHESZR 16TSSOP
標(biāo)準(zhǔn)包裝: 1,000
類型: 時鐘/頻率合成器,RF
PLL:
輸入: CMOS,TTL
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 3GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
配用: EVAL-ADF4112EBZ1-ND - BOARD EVAL FOR ADF4112
EVAL-ADF411XEBZ1-ND - BOARD EVAL FOR ADF411X NO CHIP
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 3 of 28
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 k; dBm referred to 50 ;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is as follows: B Version: 40°C to +85°C.
Table 1.
Parameter
B Version
B Chips1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
Figure 29 for input circuit.
RF Input Sensitivity
15/0
dBm min/max
RF Input Frequency
ADF4110
80/550
MHz min/max
For lower frequencies, ensure slew rate
(SR) > 30 V/s.
ADF4110
50/550
MHz min/max
Input level = 10 dBm.
ADF4111
0.08/1.2
GHz min/max
For lower frequencies, ensure SR > 30 V/s.
ADF4112
0.2/3.0
GHz min/max
For lower frequencies, ensure SR > 75 V/s.
ADF4112
0.1/3.0
GHz min/max
Input level = 10 dBm.
ADF4113
0.2/3.7
GHz min/max
Input level = 10 dBm. For lower frequencies,
ensure SR > 130 V/s.
Maximum Allowable Prescaler Output
Frequency2
165
MHz max
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
10/0
dBm min/max
RF Input Frequency
ADF4110
80/550
MHz min/max
For lower frequencies, ensure SR > 50 V/s.
ADF4111
0.08/1.4
GHz min/max
For lower frequencies, ensure SR > 50 V/s.
ADF4112
0.1/3.0
GHz min/max
For lower frequencies, ensure SR > 75 V/s.
ADF4113
0.2/3.7
GHz min/max
For lower frequencies, ensure SR > 130 V/s.
ADF4113
0.2/4.0
GHz min/max
Input level = 5 dBm.
Maximum Allowable Prescaler Output
Frequency2
200
MHz max
REFIN CHARACTERISTICS
REFIN Input Frequency
5/104
MHz min/max
For f < 5 MHz, ensure SR > 100 V/s.
Reference Input Sensitivity
0.4/AVDD
V p-p min/max
AVDD = 3.3 V, biased at AVDD/2. See Note 3.
3.0/AVDD
V p-p min/max
AVDD = 5 V, biased at AVDD/2. See Note 3.
REFIN Input Capacitance
10
pF max
REFIN Input Current
±100
A max
PHASE DETECTOR FREQUENCY4
55
MHz max
CHARGE PUMP
ICP Sink/Source
Programmable (see
High Value
5
mA typ
With RSET = 4.7 k.
Low Value
625
A typ
Absolute Accuracy
2.5
% typ
With RSET = 4.7 k.
RSET Range
2.7/10
k typ
ICP 3-State Leakage Current
1
nA typ
Sink and Source Current Matching
2
% typ
0.5 V ≤ VCP ≤ VP – 0.5 V.
ICP vs. VCP
1.5
% typ
0.5 V ≤ VCP ≤ VP – 0.5 V.
ICP vs. Temperature
2
% typ
VCP = VP/2.
LOGIC INPUTS
VINH, Input High Voltage
0.8 × DVDD
V min
VINL, Input Low Voltage
0.2 × DVDD
V max
IINH/IINL, Input Current
±1
A max
CIN, Input Capacitance
10
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
DVDD – 0.4
V min
IOH = 500 A.
VOL, Output Low Voltage
0.4
V max
IOL = 500 A.
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