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參數(shù)資料
| 型號： | ADF4107BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/20頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 7GHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | ADF4107BRUZ-REEL7-ND ADF4107BRUZ-REEL7TR |
Data Sheet
ADF4107
Rev. D | Page 9 of 20
FUNCTIONAL DESCRIPTION
REFERENCE INPUT STAGE
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
03
33
8-
0
17
100k
NC
REFIN
NC
NO
SW1
SW2
BUFFER
SW3
TO R COUNTER
POWER-DOWN
CONTROL
Figure 17. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
03
33
8-
0
18
500
1.6V
500
AGND
RFINA
RFINB
AVDD
BIAS
GENERATOR
Figure 18. RF Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and CMOS B
counters. The prescaler is programmable. It can be set in
software to 8/9, 16/17, 32/33, or 64/65. It is based on a
synchronous 4/5 core. A minimum divide ratio is possible for
fully contiguous output frequencies. This minimum is
determined by P, the prescaler value, and is given by: (P2 P).
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is as follows:
R
f
A
B
P
f
REFIN
VCO
where:
fVCO is the output frequency of external voltage controlled
oscillator (VCO).
P is the preset modulus of dual-modulus prescaler (8/9, 16/17).
B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 6-bit swallow counter (0 to 63).
fREFIN is the external reference frequency oscillator.
LOAD
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
13-BIT B
COUNTER
TO PFD
6-BIT A
COUNTER
N DIVIDER
MODULUS
CONTROL
N = BP + A
03
33
8-
0
19
Figure 19. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PHASE FREQUENCY DETECTOR AND CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 20 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse. Use of the minimum
antibacklash pulse width is not recommended. See Figure 23.
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