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參數(shù)資料
| 型號(hào)： | ADF4107BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 7GHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | ADF4107BRUZ-REEL7-ND ADF4107BRUZ-REEL7TR |
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ADF4107
Data Sheet
Rev. D | Page 18 of 20
APPLICATIONS
LOCAL OSCILLATOR FOR LMDS BASE STATION
TRANSMITTER
Figure 27 shows the ADF4107 being used with a VCO to
produce the LO for an LMDS base station.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 . A typical base station
system has either a TCXO or an OCXO driving the reference
input without any 50 termination.
To have a channel spacing of 1 MHz at the output, the 10 MHz
reference input must be divided by 10, using the on-chip
reference divider of the ADF4107.
The charge pump output of the ADF4107 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for the
system would be 45°.
Other PLL system specifications are:
KD = 5.0 mA
KV = 80 MHz/V
Loop bandwidth = 70 kHz
FPFD = 1 MHz
N = 6300
Extra reference spur attenuation = 10 dB
All of these specifications are needed and used to derive the
loop filter component values shown in Figure 27.
Figure 27 gives a typical phase noise performance of 83 dBc/Hz
at 1 kHz offset from the carrier. Spurs are better than 70 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer, and drives the RF
output terminal. A T-circuit configuration provides 50
matching between the VCO output, the RF output, and the RFIN
terminal of the synthesizer.
In a PLL system, it is important to know when the system is in
lock. In Figure 27, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be
programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock detect signal.
ADF4107
CE
CLK
DATA
LE
1000pF
REFIN
100pF
CP
MUXOUT
CP
G
ND
AG
ND
DG
ND
100pF
820pF
47pF
100pF
51Ω
1.7kΩ
7.5kΩ
100pF
18Ω
NOTES:
1. DECOUPLING CAPACITORS (0.1F/10pF) ON AVDD, DVDD, AND
VP OF THE ADF4106 AND ON VCC OF THE V956ME03 HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
SPI
-CO
M
PA
TIB
LE
S
E
R
IA
L
BUS
RSET
RFINA
RFINB
AVDD DVDD VP
FREFIN
VDD
VP
LOCK
DETECT
VCC
V956ME01
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
18Ω
100pF
RFOUT
5.1kΩ
7
15
16
8
2
14
6
5
1
9
4
3
14
2
10
51Ω
03338-
027
Figure 27. 6.3 GHz Local Oscillator Using the ADF4107
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