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參數(shù)資料
| 型號： | ADDAC80-CBI-V |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT LOW COST 24-CDIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 2µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-CDIP 側(cè)面鍍銅 |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
REV. B
–6–
ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS
ADDAC85LD
ADDAC85MIL
ADDAC87
Model
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
POWER SUPPLY REQUIREMENTS
Rated Voltages
±15, 5
V
Range
Analog Supplies
±14.5
±15.5
±14.5
±15.5
±13.5
±16.5
V
Logic Supplies
+4.5
±15.5
+4.5
+15.5
+4.5
±16.5
V
Supply Drain
7
+15 V
15
20
15
20
10
20
mA
–15 V
25
30
25
30
20
35
mA
+5 V
8
15
20
15
20
10
20
mA
TEMPERATURE RANGE
Specification
–25
+85
–55
+125
–55
+125
°C
Operating
–55
+125
–55
+125
–55
+125
°C
Storage
–55
+125
–55
+125
–65
+150
°C
NOTES
1Least Significant Bit.
2Adjustable to zero with external trim potentiometer.
3FSR means “Full-Scale Range” and is 20 V for the
± 10 V range and 10 V for the ± 5 V range.
4Gain and offset errors adjusted to zero at 25
°C.
5C
F = 0, see Figure 3a.
6Maximum with no degradation of specification, must be a constant load.
7Including 5 mA load.
85 V supply required only for CCD versions.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
+VS to Power Ground . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
–VS to Power Ground . . . . . . . . . . . . . . . . . . . . 0 V to –18 V
Digital Inputs (Pins 1 to 12) to Power Ground . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7 V
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . .
±12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . .
±12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . .
±12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . .
±24 V
Ref Out . . . . . . . . . Indefinite Short to Power Ground or +VS
*NC = CBI VERSIONS
5V – CCD VERSIONS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
(LSB) BIT 12
VREF OUT
GAIN ADJUST
+VS
COMMON
SUMMING JUNCTION
20V RANGE
10V RANGE
BIPOLAR OFFSET
REF INPUT
VOUT
–VS
NC/+VL*
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
REF
CONTROL
CIRCUIT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
6.3k
5k
ADDAC80
+
–
Figure 1. Voltage Model Function Diagram
and Pin Configuration
*NC = CBI VERSIONS
5V – CCD VERSIONS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
(LSB) BIT 12
VREF OUT
GAIN ADJUST
+VS
COMMON
SCALING NETWORK
BIPOLAR OFFSET
REF INPUT
IOUT
–VS
NC/+VL*
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
REF
CONTROL
CIRCUIT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
6.3k
2k
5k
Figure 2. Current Model Functional Diagram
and Pin Configuration
(continued)
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