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參數(shù)資料
| 型號： | ADCV08832CIMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, 8-Bit Serial I/O CMOS A/D Converter with Sample/Hold Function |
| 中文描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 259K |
| 代理商： | ADCV08832CIMX |
Timing Diagrams
(Continued)
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator struc-
ture with built-in sample-and-hold which provides for a differ-
ential analog input to be converted by a successive approxi-
mation routine.
In differential mode the voltage converted is always the
difference between the assigned “+” input terminal and the
“” input terminal. The polarity of each input terminal of the
pair indicates which line the converter expects to be the most
positive. If the assigned “+” input voltage is less than the “”
input voltage the converter responds with an all zeros output
code.
The multiplexor at the analog inputs of the converter pro-
vides for the software-configurable single-ended or differen-
tial operation. The analog signal conditioning required in
transducer-based data acquisition systems is significantly
simplified with this type of input flexibility. A single
ADCV08832 can handle ground referenced inputs, differen-
tial inputs, as well as signals with some arbitrary reference
voltage.
The input configuration is assigned during the MUX address-
ing sequence, prior to the start of a conversion. The MUX
address selects which of the analog inputs will be enabled,
and whether this input is single-ended or differential. In
addition to selecting the differential mode, the polarity may
also be selected. Channel 0 may be selected as the positive
input and channel 1 as the negative input or vice versa. This
programmability is illustrated in the MUX addressing tables.
MUX Addressing: ADCV08832
Single-Ended MUX Mode
MUX Address
Start
Bit
DIF
1
1
1
1
Channel
#
SGL/
ODD/
SIGN
0
1
0
1
+
+
Differential MUX Mode
MUX Address
Start
Bit
DIF
1
0
1
0
Channel
#
SGL/
ODD/
SIGN
0
1
0
1
+
+
Since the input configuration is under software control, it can
be modified as required before each conversion. A channel
could be treated as a single-ended, ground referenced input
for one conversion; then, it could be reconfigured as part of
a differential channel for another conversion.
The analog input voltages for each channel can range from
50mV below ground to 50mV above Vcc without degrading
conversion accuracy.
2.0 THE DIGITAL INTERFACE
An important characteristic of this converter is the serial
communication interface with the controlling processor. The
serial interface facilitates versatile operation in a small pack-
age. The small converter can be placed close to the analog
source, converting a low level signal into a noise immune bit
stream.
To understand the operation of these converters, it is best to
refer to the Timing Diagrams and Functional Block Diagram
and follow a complete conversion sequence.
1.
A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire con-
version (13 Clock Cycles). The converter is now waiting
for a start bit and its MUX assignment word.
2.
On each rising edge of the clock the data on the DI line
is clocked into the MUX address shift register. The start
bit is the first logic
″
1
″
that appears on this line (all
leading zeros are ignored). Following the start bit the
converter expects the next 2 bits to be the MUX address.
3.
A conversion begins
1
2
clock after the odd/sign bit is
latched. An interval of
1
2
clock period (where nothing
happens) is automatically inserted to allow the selected
MUX channel to settle to a final analog input value. The
DI line is ignored for the remainder of the conversion.
4.
On the falling edge of the 3rd clock. DO exits TRI-STATE
and provides a leading zero for this one clock period of
MUX settling time.
ADCV08832 Timing
DS200084-26
A
www.national.com
9
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