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參數(shù)資料
| 型號： | ADCV08832CIMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, 8-Bit Serial I/O CMOS A/D Converter with Sample/Hold Function |
| 中文描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 259K |
| 代理商： | ADCV08832CIMX |
Electrical Characteristics
(Continued)
The following specifications apply for V
CC
= 3.3V, 50% Duty Cycle, and t
r
= t
f
= 20 ns unless otherwise specified.
Boldface
limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Clock Duty Cycle
(Note 12)
t
CONV
Conversion Time (Not Including MUX
Addressing Time)
f
CLK
= 500 kHz
t
ca
Acquisition Time
t
SET-UP
Set Up Time Required from Falling CS
to Rising Clock Edge
t
HOLD
Data Input Valid after CLK
Rising Edge
t
pd1
, t
pd0
CLK Falling Edge to Output
Data Valid (Note 13)
Data MSB First
Data LSB First
t
1H
, t
0H
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z
(see TRI-STATE Test Circuit)
C
IN
Input Capacitance of CH
0
, CH
1
(Note 14)
C
IN
Input Capacitance of CLK, D1
C
OUT
Output Capacitance of Logic Outputs
D0 (in TRI-STATE)
Conditions
Typical
Limits
40
60
8
16
Units
% (min)
% (max)
1/f
CLK
μs
1/f
CLK
(max)
1
2
15
ns (min)
20
ns (min)
C
L
= 100 pF:
150
100
ns (max)
ns (max)
C
L
= 100 pF, R
L
= 10 k
35
ns
13
pF
5
pF
5
pF
Dynamic Characteristics
The following specifications apply for V
CC
= 3.3V, f
CLK
= 500 kHz, T
A
= 25C, R
SOURCE
= 25
, f
IN
= 9.6 kHz, V
IN
= 3.3V
P-P
,
non-coherent 2048 samples.
Symbol
Parameter
f
S
Sampling Rate
SNR
Signal-to-Noise Ratio (Note 16)
THD
Total Harmonic Distortion (Note 17)
SINAD
Signal-to-Noise and Distortion
ENOB
Effective Number Of Bits (Note 15)
SFDR
Spurious Free Dynamic Range
Conditions
Typical
f
CLK
/13
49.5
66
49.4
7.9
67.6
Limits
Units
ksps
dB
dB
dB
Bits
dB
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2:
Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
Note 3:
All voltages are measured with respect to GND = 0 V
DC
, unless otherwise specified.
Note 4:
When the input voltage V
at any pin exceeds the power supplies (V
<
(GND) or V
IN
>
V
,) the current at that pin should be limited to 5 mA. The 20 mA
maximum package input current rating limits the number of pins that can safely exceed V
CC
with an input current of 5 mA to four pins.
Note 5:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
,
θ
and the ambient temperature, T
. The maximum
allowable power dissipation at any temperature is P
D
= (T
JMAX
T
A
)/
θ
JA
or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 6:
Human body model, 100 pF capacitor discharged through a 1.5 k
resistor. The machine mode is a 200 pF capacitor discharged directly into each pin.
Note 7:
Typical are at T
J
= 25C and represent the most likely parametric norm.
Note 8:
Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9:
Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
Note 10:
For V
IN()
≥
V
IN(+)
the digital output will be 0000 0000. Two on-chip diodes are tied to each analog input (see Functional Block Diagram) which will
forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than V
CC
. During testing at low V
CC
levels (e.g., 2.7V), high level
analog inputs (e.g., 3.3V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode; this means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code
will be correct. Exceeding the range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V
DC
to 3.30 V
DC
input
voltage range will therefore require a minimum supply voltage of 3.25 V
DC
over temperature variations, initial tolerance and loading.
Note 11:
Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (3.3V
DC
) and the remaining off channel tied low (0 V
DC
), total current flow through the off channel
is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channel is again measured. The two cases
considered for determining the on channel leakage current are the same except total current flow through the selected channel is measured.
Note 12:
A 40% to 60% duty cycle range insures proper operation at all clock frequencies.
Note 13:
Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow for comparator
response time.
A
www.national.com
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