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參數(shù)資料
| 型號： | ADCMP582BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR PECL UFAST 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補(bǔ)充型，PECL |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 10mV @ ±5V |
| 電流 - 輸入偏壓（最小值）： | 30µA @ ±5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 44mA @ 5V |
| 電流 - 靜態(tài)（最大值）： | 8mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 60dB CMRR，75dB PSRR |
| 傳輸延遲（最大）： | 0.18ns |
| 磁滯： | 1mV |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADCMP582BCPZ-ND - BOARD EVALUATION ADCMP582BCP |
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 13 of 16
COMPARATOR HYSTERESIS
Adding hysteresis to a comparator is often desirable in a noisy
environment or when the differential inputs are very small or
slow moving. The transfer function for a comparator with
hysteresis is shown in Figure 28. If the input voltage approaches
the threshold from the negative direction, the comparator
switches from a low to a high when the input crosses +VH/2.
The new switching threshold becomes VH/2. The comparator
remains in the high state until the threshold VH/2 is crossed
from the positive direction. In this manner, noise centered on
0 V input does not cause the comparator to switch states unless
it exceeds the region bounded by ±VH/2.
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to
the input. A limitation of this approach is that the amount
of hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and can even
reduce overall stability in some cases.
OUTPUT
INPUT
0V
0
1
+VH
2
–VH
2
0
46
72
-02
8
Figure 28. Comparator Hysteresis Transfer Function
The ADCMP58x family of comparators offers a programmable
hysteresis feature that can significantly improve the accuracy
and stability of the desired hysteresis. By connecting an external
pull-down resistor from the HYS pin to VEE, a variable amount
of hysteresis can be applied. Leaving the HYS pin disconnected
disables the feature, and hysteresis is then less than 1 mV, as
specified. The maximum range of hysteresis that can be applied
by using this method is approximately ±70 mV.
Figure 29 illustrates the amount of applied hysteresis as a
function of the external resistor value. The advantage of
applying hysteresis in this manner is improved accuracy,
stability, and reduced component count. An external bypass
capacitor is not required on the HYS pin, and it would likely
degrade the jitter performance of the device.
The hysteresis pin can also be driven by a current source.
It is biased approximately 400 mV above VEE and has an
internal series resistance of approximately 600 Ω.
80
0
1
10k
RHYS CONTROL RESISTOR ()
C
O
M
P
A
R
A
T
O
R
H
YST
ER
ES
IS
(m
V)
70
60
50
40
30
20
10
100
1k
04
67
2-
0
29
Figure 29. Comparator Hysteresis vs. RHYS Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENT
As with many high speed comparators, a minimum slew rate
requirement must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This oscil-
lation is due in part to the high input bandwidth of the comparator
and the feedback parasitics inherent in the package. A
minimum slew rate of 50 V/μs should ensure clean output
transitions from the ADCMP58x family of comparators.
The slew rate may be too slow for other reasons. The extremely
high bandwidth of these devices means that broadband noise
can be a significant factor when input slew rates are low. There
is 120 μV of thermal noise generated over the bandwidth of the
comparator by the two 50 Ω terminations at room temperature.
With a slew rate of only 50 V/μs, the inputs are inside this noise
band for over 2 ps, rendering the comparator’s jitter performance of
200 fs irrelevant. Raising the slew rate of the input signal and/or
reducing the bandwidth over which that resistance is seen at the
input can greatly reduce jitter. Devices are not characterized this
way but simply bypassing a reference input close to the package
can reduce jitter 30% in low slew rate applications.
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