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參數(shù)資料
| 型號： | ADCMP582BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR PECL UFAST 16LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補充型，PECL |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 10mV @ ±5V |
| 電流 - 輸入偏壓（最小值）： | 30µA @ ±5V |
| 電流 - 輸出（標準）： | 44mA @ 5V |
| 電流 - 靜態(tài)（最大值）： | 8mA |
| CMRR, PSRR（標準）： | 60dB CMRR，75dB PSRR |
| 傳輸延遲（最大）： | 0.18ns |
| 磁滯： | 1mV |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADCMP582BCPZ-ND - BOARD EVALUATION ADCMP582BCP |
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 11 of 16
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP58x family of comparators is designed for very
high speed applications. Consequently, high speed design
techniques must be used to achieve the specified performance.
It is critically important to use low impedance supply planes,
particularly for the negative supply (VEE), the output supply
plane (VCCO), and the ground plane (GND). Individual supply
planes are recommended as part of a multilayer board. Provid-
ing the lowest inductance return path for the switching currents
ensures the best possible performance in the target application.
It is also important to adequately bypass the input and output
supplies. A 1 μF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.1 μF bypass capacitors should
be placed as close as possible to each of the VEE, VCCI, and VCCO
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be strictly avoided to maximize the
effectiveness of the bypass at high frequencies.
ADCMP58x FAMILY OF OUTPUT STAGES
Specified propagation delay dispersion performance is achieved
by using proper transmission line terminations. The outputs of
the ADCMP580 family comparators are designed to directly
drive 400 mV into 50 Ω cable or microstrip/stripline transmis-
sion lines terminated with 50 Ω referenced to the proper return.
The CML output stage for the ADCMP580 is shown in the
simplified schematic diagram in Figure 24. Each output is
back-terminated with 50 Ω for best transmission line matching.
The outputs of the ADCMP581/ADCMP582 are illustrated in
Figure 25; they should be terminated to 2 V for ECL outputs of
ADCMP581 and VCCO 2 V for PECL outputs of ADCMP582.
As an alternative, Thevenin equivalent termination networks
can also be used. If these high speed signals must be routed
more than a centimeter, either microstrip or stripline techniques
are required to ensure proper transition times and to prevent
excessive output ringing and pulse width-dependent propagation
delay dispersion.
Q
16mA
50
Q
GND
VEE
046
72
-02
4
Figure 24. Simplified Schematic Diagram of the ADCMP580 CML Output Stage
GND/VCCO
VEE
Q
04
67
2-
0
25
Figure 25. Simplified Schematic Diagram of the
ADCMP581/ADCMP582 ECL/PECL Output Stage
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/LE) are active low for latch mode and are
internally terminated with 50 Ω resistors to the VTT pin. When
using the ADCMP580, VTT should be connected to ground.
When using the ADCMP581, VTT should be connected to 2 V.
When using the ADCMP582, VTT should be connected externally
to VCCO 2 V, preferably with its own low inductance plane.
When using the ADCMP580, the latch function can be disabled
by connecting the LE pin to VEE with an external pull-down
resistor and by leaving the LE pin to ground. To prevent excessive
power dissipation, the resistor should be 1 kΩ for the ADCMP580.
When using the ADCMP581 comparators, the latch can be
disabled by connecting the LE pin to VEE with an external 750 Ω
resistor and leaving the LE pin connected to 2 V. The idea is to
create an approximate 0.5 V offset using the internal resistor as
half of the voltage divider. The VTT pin should be connected as
recommended.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADCMP582BCPZ-WP | 功能描述:IC COMPARATOR PECL UFAST 16LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:帶電壓基準 元件數(shù):4 輸出類型:開路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標準）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產(chǎn)品目錄頁面:1386 (CN2011-ZH PDF) |
| ADCMP600 | 制造商:Analog Devices 功能描述:- Tape and Reel |
| ADCMP600_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V |
| ADCMP600BKSZ-R2 | 功能描述:IC COMP TTL/CMOS 1CHAN SC70-5 RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP600BKSZ-REEL7 | 功能描述:IC COMP TTL/CMOS 1CHAN SC70-5 RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:帶電壓基準 元件數(shù):4 輸出類型:開路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標準）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產(chǎn)品目錄頁面:1386 (CN2011-ZH PDF) |
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