參數(shù)資料
型號: ADCLK925BCPZ-WP
廠商: Analog Devices Inc
文件頁數(shù): 1/16頁
文件大小: 0K
描述: IC CLOCK/DATA BUFFER 1:2 16LFCSP
標(biāo)準(zhǔn)包裝: 50
系列: SIGe
類型: 扇出緩沖器(分配),數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
輸入: 時(shí)鐘
輸出: ECL,NECL,PECL
頻率 - 最大: 7.5GHz
電源電壓: 2.375 V ~ 3.63 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 托盤 - 晶粒
配用: ADCLK925/PCBZ-ND - BOARD EVAL FOR ADCLK925 16LFCSP
Ultrafast SiGe
ECL Clock/Data Buffers
ADCLK905/ADCLK907/ADCLK925
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2007 Analog Devices, Inc. All rights reserved.
FEATURES
95 ps propagation delay
7.5 GHz toggle rate
60 ps typical output rise/fall
60 fs random jitter (RJ)
On-chip terminations at both input pins
Extended industrial temperature range: 40°C to +125°C
2.5 V to 3.3 V power supply (VCC VEE)
APPLICATIONS
Clock and data signal restoration and level shifting
Automated test equipment (ATE)
High speed instrumentation
High speed line receivers
Threshold detection
Converter clocking
GENERAL DESCRIPTION
The ADCLK905 (one input, one output), ADCLK907 (dual one
input, one output), and ADCLK925 (one input, two outputs) are
ultrafast clock/data buffers fabricated on the Analog Devices, Inc.,
proprietary XFCB3 silicon germanium (SiGe) bipolar process.
The ADCLK905/ADCLK907/ADCLK925 feature full-swing
emitter coupled logic (ECL) output drivers. For PECL (positive
ECL) operation, bias VCC to the positive supply and VEE to ground.
For NECL (negative ECL) operation, bias VCC to ground and
VEE to the negative supply.
The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate,
10 Gbps data rate, and 60 fs random jitter (RJ).
The inputs have center tapped, 100 Ω, on-chip termination
resistors. A VREF pin is available for biasing ac-coupled inputs.
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC 2 V for a total
differential output swing of 1.6 V.
The ADCLK905/ADCLK907/ADCLK925 are available in
16-lead LFCSP packages.
TYPICAL APPLICATION CIRCUITS
D
Q
VCC
VEE
VT
Q
VREF
0
631
8-
0
01
Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer
D1
Q1
VCC
VEE
VT1
Q1
VREF1
D2
Q2
VCC
VEE
VT2
D2
VREF2
Q2
06
31
8-
0
02
Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer
D
VCC
VEE
VT
VREF
Q1
Q2
06
31
8-
00
3
Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer
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