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參數(shù)資料
| 型號： | ADC9708CCN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 6-Channel 8-Bit uP Compatible A/D Converter |
| 中文描述： | 6-CH 8-BIT SINGLE-SLOPE ADC, SERIAL ACCESS, PDIP16 |
| 封裝： | DIP-16 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 175K |
| 代理商： | ADC9708CCN |
Electrical Characteristics
Over recommended operating conditions, V
CC
e
5.0V,
b
55
§
C
s
T
A
s
a
125
§
C for ADC9708CMJ and 0
§
C
s
T
A
s
a
70
§
C for
ADC9708CCJ or ADC9708CCN; unless otherwise specified. (Continued)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limit
(Note 11)
Units
(Limit)
I
CC
C
IN
C
OUT
Power Supply Current
V
CC
e
5V to 15V, I0
e
0
7.5
15
mA (max)
Input Capacitance
3.0
pF
Comparator Output Capacitance
5.0
pF
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the
Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device
is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified.
Note 3:
V
REF
should not exceed V
CC
b
2V.
Note 4:
Conversion accuracy is defined as the deviations from a straight line drawn between the points defined by channel address 000 (0 scale) and channel
address 111 (full scale) for all channels.
Note 5:
Linearity is defined as the deviation from a straight line drawn between the 0 and full scale points for each channel.
Note 6:
Power supply rejection ratio is defined as the conversion error contributed by power supply voltage variations while resolving mid scale on any channel.
Note 7:
Cross Talk between channels
e
20 log
D
V
CH
D
V
I
.
Note 8:
Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex. when any inputs or
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
(maximum junction
temperature),
i
JA
(package junction to ambient thermal resistance), and T
A
(ambient temperature). The maximum allowable power dissipation at any temperature
is P
Dmax
e
(T
Jmax
b
T
A
)/
i
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
e
150
§
C, and the typical thermal
resistance (
i
JA
) for board mounting follow:
ADC9708CCN
62
§
C/W
ADC9708CCJ, ADC9708CMJ
58
§
C/W
Note 9:
Human body model, 100 pF discharged through a 1.5 k
X
resistor.
Timing Diagram
TL/H/10409–7
FIGURE 1. Equivalent Timing Waveform for
Test Circuits and Applications
Note 10:
Typicals are at
a
25
§
C and represent most likely parametric norm.
Note 11:
Tested limits are guaranteed to National’s AOQL (Average Outgo-
ing Quality Level).
Test Circuits
Input Timing:
TL/H/10409–8
t
A
l
400
m
s
V
REF
e
#
3.3 k
X
2 k
X
a
3.3 k
X
J
5V
e
3.1
I
R
e
5
b
3.1
100 k
X
e
19
m
A
t
R
l
max
e
full scale ramp time
e
0.01
c
10
b
6
19
c
10
b
6
c
3.1
e
1.6 ms
Note:
For evaluation purposes,the ramp start timing generation can be im-
plemented with an LM555 timer (astable operation) or MPU evaluation kit,
and a time interval meter for ramp time measurement. The TIM meter will
measure the time between to 0 to 1 transition of the ramp start and the 1 to
0 transition of the ramp stop. The ramp stop is open collector, and must
have an external pull-up resistor to V
CC
.
FIGURE 2. Slow Speed Evaluation Circuit
for Ratiometric Operation
3
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