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converter. Without the error-correction technique, it
would be necessary that all the components in the
ADC5020/ ADC5030 — the difference amplifier, the
switched-gain amplifier, and the 8-bit flash A/D con-
verter — be accurate and linear to an 18-bit level.
While such a design might be possible to realize on a
laboratory benchtop, it would be clearly impractical to
achieve in production. The key to the ADC5020/
ADC5030’s conversion scheme is the 18-bit-linear D/A
converter, which serves as a reference element for the
conversion passes as well as for the error-correction
mechanism.
The ADC5020/ADC5030 has a tri-state output struc-
ture. Users can enable the eight MSBs, the eight mid-
dle bits, the two LSBs, or all bits by using the High-
Byte Enable, Mid-Byte Enable, or the Low-Byte Enable
pins (all three are active low). This feature makes it
possible to transfer data from the ADC5020/ADC5030
to an 8-bit microprocessor bus. However, to prevent
the coupling of high frequency noise from the micro-
processor bus into the A/D converter, the output data
must be buffered (see Figure 6).
TYPICAL APPLICATION
Figure 6 shows a typical application circuit for the
ADC5020/ADC5030 A/D converter. This circuit pro-
vides simultaneous sampling for two professional
audio analog-input channels. Simultaneous sampling
is a necessity in conversion systems in which the
phase, as well as amplitude relationship between dif-
ferent signals, is an important parameter. One example
is in seismic measurements where it is crucial to know
the phase relationship between the signals generated
by different sensors. Another application where the
phase and amplitude relationships are critical is profes-
sional digital audio, described in Figure 6. This applica-
tion circuit performs simultaneous sampling by “freez-
ing” the signal levels of both analog-input channels at
the same instant of time. The amplitude relationship is
maintained by the input Programmable Gain Amplifiers
that are operated differentially to eliminate the possibili-
ty of errors arising from common mode voltages. The
Anti-Aliasing Filters of Figure 6 reduce the out-of-band
products coming in the front end that would mix with
the sampling frequency and create audible in-band by-
products.
A pair of low-noise, low-distortion Sample-and-Hold
Amplifiers that have been optimized for audio band-
widths to obtain 18-bit linearity, Analogic’s SHA2410s
simultaneously sample the analog inputs and multiplex
these signal levels to the buffer stage. A high input
impedance buffer stage is required following a multi-
plexer to minimize the inherent nonlinearities of the
switch-on-resistance with respect to current variations.
The ADC5020 sequentially digitizes the two channels
and transmits the buffered data to the minicomputer or
microprocessor. The data buffer is necessary to pre-
vent the coupling of high frequency noise from the pro-
cessor bus into the A/D converters. Because the
SHA2410s provide the sample-and-hold function in
this circuit, the ADC5030, which does not include a
sample-and-hold amplifier, is an appropriate choice.
+
–
8-Bit
A/D Converter
+
–
6-Bit
A/D Converter
A/D 6-Bit
Gate
D/A12-Bit
A18-Bit
High
Mid
Low
OD/A
B1, B1-B8
B9-B16
B17, B18
A = 0.2
From
SAmplifier
A = 2
Switched-Gain
Amplifier
A = 2
SAmplifier
A = 32
A = 3.2
A = 3.2
From
PFrom D/A
From
Difference
Amplifier
PFrom D/A
Amplifier
(a)
(b)
(c)
Figure 5. Operating Principle of the ADC5020/ADC5030.