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參數(shù)資料
| 型號(hào)： | ADC5020-M2C |
| 元件分類(lèi)： | ADC |
| 英文描述： | Analog to Digital Converter |
| 中文描述： | 模數(shù)轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大小： | 107K |
| 代理商： | ADC5020-M2C |
Layout Considerations
Because of the ADC5020/ADC5030 A/D converter’s
extremely high resolution, it is necessary to pay careful
attention to the printed circuit layout for the device. It is,
for example, important to separate the analog and digi-
tal grounds and to return them separately to the sys-
tem power supply. Digital grounds are often noisy or
“glitchy”, and these glitches can have adverse effects
on the performance of the ADC5020/ADC5030 if they
are introduced to the analog portions of the A/D con-
verter’s circuitry. At 18-bit resolution, the size of the
voltage step between one code transition and the suc-
ceeding one is only 38 μV, so it is evident that any
noise in the analog ground return can result in erro-
neous or missing codes. It is therefore important to
configure a low-impedance ground-plane return on the
printed circuit board. Note that the ground-potential
metal case used for the ADC5020/ADC5030 provides
shielding against electromagnetic interference on five
sides and against electrostatic interference on six
sides.
PRINCIPLES OF OPERATION
To understand the operating principles of the
ADC5020/ADC5030 A/D converter, refer to Figure 5.
The simplified block diagrams in paths a, b, and c in
Figure 5 illustrate the three successive passes in the
sub-ranging conversion scheme of the ADC5020/
ADC5030. For all three passes, the lines labeled
“From Input” come either from the output of the sam-
ple-and-hold amplifier (in the ADC5020) or from the
output of the input buffer amplifier (in the ADC5030).
All three passes use the same 8-bit flash A/D converter
with the first and second pass utilizing only the first six
bits. In the first pass (a), a switched-gain amplifier at-
tenuates the input signal by a factor of five. It thus con-
verts the 10V full scale range of the input to the 2V full
scale range of the 6-bit flash A/D converter. The 6-bit
A/D converter then digitizes the six MSBs of the input
signal. The outputs of the A/D converter drive the six
MSBs of the D/A converter. The six output lines of the
A/D converter are actually latched into the logic circuit-
ry of a specialized gate array, which drives the input
lines of the D/A converter.
In the second pass (b), a difference amplifier subtracts
the D/A converter’s output voltage from the input volt-
age, then amplifies this difference by a factor of 3.2.
The switched-gain amplifier now has a gain of two, and
thus amplifies the difference voltage further. The output
of the switched-gain amplifier again provides the input
signal for the 8-bit flash A/D converter. The A/D con-
verter’s outputs are latched into the gate array which
supplies the next lower-order bits of the D/A converter.
In the gate array, the A/D converter’s MSB in the sec-
ond pass “overlaps” the LSB from the first pass. The
resolution of the A/D conversion in the second pass is
thus 11 bits (not 12).
In the third pass (c), the gain-of-3.2 difference amplifier
subtracts the D/A converter’s output voltage from the
input voltage. In this pass, an amplifier with a gain of
32 provides additional amplification of the difference
signal. The eight outputs of the 8-bit flash A/D convert-
er are latched into the gate array; the MSB of this con-
version cycle “overlaps” the LSB of the previous cycle.
The effective resolution of the conversion is thus 6 + 5
+ 7, or 18 bits. Using the “overlap” structure, logic cir-
cuitry in the gate array adds the digital words produced
in the three passes and produces the corrected output
word. This digital error-correction technique thus pro-
vides an output word that is accurate and linear to
within the full resolution of the A/D converter. The
method corrects for any gain and linearity errors in the
amplifying circuitry, as well as in the 8-bit flash A/D
t = N
t = N + 1
0.05 to 2
μ
s
1.94
μ
s
Aperture Delay
20 ns typ.
N – 1 Data Valid
N Data Valid
Trigger
EOC
S/H
Data
6.94
μ
s
5
μ
s
Figure 3. ADC5020/ADC5030 Timing Diagram.
(2.0.1"
(73.00"
74 73 72626160 57 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38
1 2 3 12 14 15 29 30 3132 3637
ADCTop View
(104.00"
Offset
Gain
1.32" (3.35 mm)
1.19" (3.02 mm)
(10.44"
0.2" min
(5.0.2"
Pin Spacing 0.1" (2.54 mm)
Figure 4. ADC5020/ADC5030 Outline Drawing &
Pinouts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADC5020-M2S | Analog to Digital Converter |
| ADC5020-M4C | Analog to Digital Converter |
| ADC5020-M4S | Analog to Digital Converter |
| ADC5030-M1C | Half-/Full-Bridge N-Channel Power MOSFET Drivers |
| ADC5030-M1S | Half-/Full-Bridge N-Channel Power MOSFET Drivers; Package: SO; No of Pins: 24; Temperature Range: -40°C to +85°C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC5020-M2S | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Analog to Digital Converter |
| ADC5020-M4C | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Analog to Digital Converter |
| ADC5020-M4S | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Analog to Digital Converter |
| ADC5030-M1C | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Analog to Digital Converter |
| ADC5030-M1S | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Analog to Digital Converter |
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