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參數(shù)資料
| 型號： | ADC14071CIVBH |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 7 MSPS, 380 mW A/D Converter |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大小： | 427K |
| 代理商： | ADC14071CIVBH |
Applications Information
(Continued)
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails.
For proper operation, all inputs should not go
more than 300 mV beyond the supply rails (more than 300
mV below the ground pins or 300 mV above the supply pins).
Exceeding these limits on even a transient basis may cause
faulty or erratic operation. It is not uncommon for high speed
digital circuits (e.g., 74F and 74AC devices) to exhibit over-
shoot or undershoot that goes above the power supply or
more than a volt below ground. A resistor of about 50
to
100
in series with the offending digital input will eliminate
the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up.
Be careful not to overdrive the inputs of the ADC14071 with
a device that is powered from supplies outside the range of
the ADC14071 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through DR V
and DR GND. These large charging
current spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem.
Additionally, bus capacitance beyond the specified 20 pF/pin
will cause t
to increase, making it difficult to properly latch
theADC output data. The result could, again, be an apparent
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC14071, which reduces the energy coupled back into the
converter output pins by limiting the output current.Areason-
able value for these resistors is 47
.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the in-
put alternates between 14 pF and 5 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade perfor-
mance. A small series resistor at each amplifier output and a
capacitor across the analog inputs (as shown in Figures 6, 7)
will improve performance. The LM6172 has been success-
fully used to drive the analog inputs of the ADC14071.
Also, it is important that te signals at the two inputs have ex-
actly the same amplitude and be exactly 180 out of phase
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the effec-
tive phase between these two signals. Remember that an
operational amplifier operated in the non-inverting configura-
tion will exhibit more time delay than will the same device op-
erating in the inverting configuration.
Operating with the reference pins outside of the speci-
fied range.
As mentioned in Section 1.2, V
REF
should be in
the range of
1.0V
≤
V
REF
≤
2.7V.
Operating outside of these limits could lead to performance
degradation.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace.
This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR performance.
DS101101-29
FIGURE 9. Isolating the ADC Clock from other Circuitry
with A Clock Tree
A
www.national.com
17
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