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參數(shù)資料
| 型號(hào)： | ADC14071CIVBH |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | ADC |
| 英文描述： | 14-Bit, 7 MSPS, 380 mW A/D Converter |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大?。?/td> | 427K |
| 代理商： | ADC14071CIVBH |
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Functional Description
Operating on a single +5V supply, the ADC14071 uses a
pipelined architecture and has error correction circuitry to
help ensure maximum performance.
Balanced analog signals are digitized to 14 bits. Each of
these input signals should have a peak-to-peak voltage
equal to the input reference voltage, V
, and can be cen-
tered around V
/2. Table 1 and Table 2 indicate the input
to output relationship of theADC14071.As indicated in Table
2 biasing one input to V
/2 and driving the other input with
its full range signal results in a 6 dB reduction of the output
range, limiting it to the range of
1
4
to
3
4
of the minimum out-
put range obtainable if both inputs were driven with compli-
mentary signals.
Section 1.3 SIGNAL INPUTS explains how to avoid this sig-
nal reduction.
TABLE 1. Input to Output Relationship— Differential
Input
V
IN
+
0
V
IN
V
REF
Output
00 0000 0000 0000
01 0000 0000 0000
10 0000 0000 0000
11 0000 0000 0000
11 1111 1111 1111
0.25*V
REF
0.50*V
REF
0.75*V
REF
V
REF
0.75*V
REF
0.50*V
REF
025*V
REF
0
TABLE 2. Input to Output Relationship— Single-Ended
Input
V
IN
+
0
V
IN
V
REF
/2
V
REF
/2
V
REF
/2
V
REF
/2
V
REF
/2
Output
01 0000 0000 0000
01 1000 0000 0000
10 0000 0000 0000
10 1000 0000 0000
11 0000 0000 0000
0.25*V
REF
0.50*V
REF
0.75*V
REF
V
REF
The output word rate is the same as the clock frequency,
which can be between 25kSPS and 8 MSPS (typical). The
analog input voltage is acquired at the rising edge of the
clock and the digital data for that sample is delayed by the
pipeline for 12 clock cycles.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 20 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC14071:
4.75V
≤
V
A
≤
5.25V
V
D
= V
A
2.7
≤
DR V
D
≤
V
D
25 kHz
≤
f
CLK
≤
8 MHz
1.0V
≤
V
REF
≤
2.7V
1.1 ANALOG INPUTS
The ADC14071 has two analog signal inputs, V
+
and V
.
These two pins form a differential input. There is one refer-
ence input pin, V
REF
.
1.2 REFERENCE INPUT
TheADC14071 is designed to operate with a 2.0V reference,
but performs well with reference voltages in the range of
1.0V to 2.7V. Reducing the reference voltage below 1.0V will
decrease the signal-to-noise ratio (SNR) of the ADC14071.
Increasing the reference voltage (and the input signal swing)
beyond 2.7V will degrade THD.
It is very important that all grounds associated with the refer-
ence voltage and the input signal make connection to the
analog ground plane at a single point to minimize the effects
of noise currents in the ground path.
The reference bypass pins (V
+
BY, V
BY and V
and V
BY) are for bypass purposes only. Bypass
each of these pins to AGND with 0.1μF capacitors. DO NOT
LOAD these pins.
1.3 SIGNAL INPUTS
The signal inputs are V
IN
+
and V
IN
. The input signal, V
IN
, is
defined as
V
IN
= (V
IN
+
) – (V
IN
).
Figure 3 shows the expected input signal range.
Note that the nominal input common mode voltage is 1.0V.
This assumes that the input signals run between the limits of
AGND and 2V with V
= 2.0V. As the input signal V
in-
creases above 4 V
, the input common mode range should
become V
/2. The Peaks of the input signals should never
exceed the voltage described as
Peak Input Voltage = V
A
2.0V
to
maintain
signal
integrity
performance.
and
THD
and
SINAD
The ADC14071 performs best with a differential input cen-
tered around half the reference voltage, V
. The
peak-to-peak voltage swing at both V
+
and V
should not
exceed the value of the reference voltage or the output data
will be clipped. The two input signals should be exactly 180
out of phase from each other and of the same amplitute to
avoid a reduction in the output amplitude. For angular devia-
tions of up to 10 from these two signals being 180 out of
phase, the full scale error in LSB can be described as
E
FS
= dev
1.79
.
Where dev is the angular difference between the two signals
having a 180 relative phase relationship to each other, as
shown in Figure 4 Drive the analog inputs with a source im-
pedance less than 100
.
DS101101-24
FIGURE 3. Expected Input Signal Range
A
www.national.com
12
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