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參數(shù)資料
| 型號： | ADC12281 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter(12位20 MSPS單端輸入管線式A/D轉(zhuǎn)換器) |
| 中文描述： | 12位，20 MSPS的單端輸入，流水線A / D轉(zhuǎn)換器（12位20 MSPS的單端輸入管線式的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 322K |
| 代理商： | ADC12281 |
DC and Logic Electrical Characteristics
(Continued)
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
= V
= V
I/O = +5V, PD = +5V, V
REF
= +2.0V,
f
= 20 MHz, 3 V
P-P
at 50% duty cycle, C
= 25 pF/pin. After Auto-Cal.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C (Notes 7, 8, 9).
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
V
OH
Logical “1” Output Voltage
V
OL
Logical “0” Output Voltage
I
OUT
= 1 mA
I
OUT
= 1.6 mA
V
OUT
= 3V or 5V
V
OUT
= 0V
4
V (min)
V (max)
nA
nA
0.4
I
OZ
TRI-STATE Output Current
100
100
+I
SC
Output Short Circuit Source
Current
Output Short Circuit Sink Current
POWER SUPPLY CHARACTERISTICS
V
D
I/O = 3V, V
OUT
= 0V
29
mA
I
SC
V
D
I/O = 3V, V
OUT
= V
D
28
mA
I
A
Analog Supply Current
PD = DGND (active)
PD = V
D
I/O (power-down mode)
PD = DGND (active)
PD = V
D
I/O (power-down mode)
PD = DGND (active)
PD = V
D
I/O (power-down mode)
85
3.5
3.6
1
443
20
100
mA (max)
mA
mA (max)
mA
mW (max)
typ
I
D
Digital Supply Current
6
Total Power Consumption
530
AC Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
= V
= V
I/O = +5V, PD = +5V, V
REF
= +2.0V,
f
= 20 MHz, 3 V
P-P
at 50% duty cycle, C
= 25 pF/pin. After Auto-Cal.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C (Notes 7, 8, 9).
Symbol
Parameter
Conditions
Typical
(Note 10)
0.5
Limits
(Note 11)
Units
(Limits)
MHz (min)
MHz (max)
Clock
Cycles
ns (max)
ns
ns
T
CLK
T
CLK
T
CLK
T
CLK
T
CLK
T
CLK
f
CLK
Conversion Clock (CLOCK) Frequency
20
t
CONV
Conversion Latency
10
t
OD
I
OZ
t
OE
t
WCAL
t
RDYC
t
CAL
t
WPD
t
RDYPD
t
PD
Data Output Delay after Rising CLK Edge
Data Outputs into TRI-STATE Mode
Data Outputs Active after TRI-STATE
Calibration Request Pulse Width
Ready Low after CAL Request
Calibration Cycle
Power-Down Pulse Width
Ready Low after PD Request
Power-Down Mode Exit Cycle
5
17
16
10
3
3
4000
3
3
4000
Note 1:
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test condi-
tions.
Note 2:
All voltages are measured with respect to GND = AGND = DGND = DGND I/O = 0V, unless otherwise specified.
Note 3:
When the input voltage at any pin exceeds the power supplies (that is, V
IN
<
AGND or V
IN
>
V
A
, V
D
or V
D
I/O), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4:
The absolute maximum junction temperature (T
JMAX
) for this device is 150C. The maximum allowable power dissipation is dictated by T
JMAX
, the
junction-to-ambient thermal resistance (
θ
), and the ambient temperature (T
), and can be calculated using the formula P
MAX = (T
– T
) /
θ
. In the 32-pin
TQFP,
θ
is 79C/W, so P
MAX = 1,582 mW at 25C and 949 mW at the maximum operating ambient temperature of 75C. Note that the power dissipation of this
device under normal operation will typically be about 125 mW (typical power dissipation + 20 mW TTL output loading). The values for maximum power dissipation
listed above will be reached only when the ADC12281 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply volt-
ages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5:
Human body model is 100 pF capacitor discharged through a 1.5 k
resistor. Machine model is 220 pF discharged through 0
.
Note 6:
See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
A
www.national.com
6
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