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參數(shù)資料
| 型號： | ADC12281 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter(12位20 MSPS單端輸入管線式A/D轉(zhuǎn)換器) |
| 中文描述： | 12位，20 MSPS的單端輸入，流水線A / D轉(zhuǎn)換器（12位20 MSPS的單端輸入管線式的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 322K |
| 代理商： | ADC12281 |
Applications Information
(Continued)
6.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails.
For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital circuits (e.g., 74F and 74AC devices) to exhibit
overshoot or undershoot that goes above the power supply
or more than a volt below ground. A resistor of about 50
to
100
in series with the offending digital input will eliminate
the problem.
Do not allow input voltages to exceed the supply voltage dur-
ing power up.
Be careful not to overdrive the inputs of the ADC12281 with
a device that is powered from supplies outside the range of
the ADC12281 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
D
I/O and DGND I/O. These large charging
current spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem. The digital data outputs should be buffered (with
74ACQ541, for example). Dynamic performance can also be
improved by adding series resistors at each digital output,
close to the ADC12281, which reduces the energy coupled
back into the converter output pins by limiting the output cur-
rent. A reasonable value for these resistors is 47
.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.2, the capacitance seen at the in-
put alternates between 12 pF and 28 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade perfor-
mance. The CLC409 has been found to be a good amplifier
to drive the ADC12281. A small series resistor at the ampli-
fier output, followed by a capacitor to ground (as shown in
Figure 5), will improve performance.
Operating with the reference pins outside of the speci-
fied range.
As mentioned in Section 1.1, V
should be in
the range of 1.8V
≤
V
≤
2.2V. Operating outside of these
limits could lead to output distortion.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace.
This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR and SINAD performance.
A
www.national.com
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相關代理商/技術參數(shù) |
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| ADC12281CIVT | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D Converter |
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| ADC122S021CIMM/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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