參數(shù)資料
型號(hào): ADC12191CIVT
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32
封裝: TQFP-32
文件頁(yè)數(shù): 14/16頁(yè)
文件大?。?/td> 278K
代理商: ADC12191CIVT
Applications Information
(Continued)
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected be-
tween the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
Figure 6gives an example of a suitable layout.All analog cir-
cuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
All ground connections should have a low inductance path to
ground.
6.0 Layout and Grounding
The ADC12191 can achieve impressive dynamic perfor-
mance. To achieve the best dynamic performance with the
ADC12191, the clock source driving the CLK input must be
free of jitter. For best ac performance, isolating the ADC
clock from any digital circuitry should be done with adequate
buffers, as with a clock tree. See Figure 7
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce phase noise (jitter) into the clock
signal, which can lead to increased distortion. Even lines
with 90 crossings have capacitive coupling, so try to avoid
even these 90 crossings of the clock line.
7.0 Common Application Pitfalls
Driving the inputs (analog or digital) beyond the power
supply rails.
For proper operation, all inputs should not go
more than 300mV beyond the supply rails (more than
DS101040-24
FIGURE 6. Layout example
DS101040-25
FIGURE 7. Isolating the ADC clock from other circuitry
with a clock tree.
A
www.national.com
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