參數(shù)資料
型號: ADC12138CIWM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 1.2UF/100VDC METAL POLY CAP
中文描述: 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO28
封裝: SSOP-28
文件頁數(shù): 8/41頁
文件大?。?/td> 1085K
代理商: ADC12138CIWM
DC and Logic Electrical Characteristics
(Continued)
The following specifications apply for (V
+
= V
+ = V
+ = +5V, V
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
+ = V
+ = +3.3V, V
+ = +2.5V and fully-differential input with fixed 1.250V
common-mode voltage), V
= 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
and V
REF
+
25
, f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified.
Boldface limits apply for T
A
= T
J
=
T
MIN
to T
MAX
;
A
= T
J
= 25C. (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note
10)
V
+
= V
A
+ =
V
D
+ = 3.3V
Limits
(Note 11)
V
+
= V
A
+ =
V
D
+ = 5V
Limits
(Note 11)
Units
(Limits)
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
I
SC
Output Short
Circuit Sink
Current
POWER SUPPLY CHARACTERISTICS
I
D
+
Digital Supply
Current
V
OUT
= V
D
+
16
mA
1.5
2.5
mA (max)
μA
μA
mA (max)
μA
μA
CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
600
20
I
A
+
Positive Analog
Supply Current
3.0
4.0
CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
10
0.1
I
REF
Reference Input
Current
CS = HIGH, Powered Down, CCLK on
CS = HIGH, Powered Down, CCLK off
70
0.1
μA
μA
AC Electrical Characteristics
The following specifications apply for (V
+
= V
+ = V
+ = +5V, V
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
+ = V
+ = +3.3V, V
+ = +2.5V and fully-differential input with fixed 1.250V
common-mode voltage), V
= 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
and V
REF
+
25
, f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified.
Boldface limits apply for T
A
= T
J
=
T
MIN
to T
MAX
;
A
= T
J
= 25C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note
10)
10
1
10
0
Limits
(Note
11)
5
Units
(Limits)
f
CK
Conversion Clock
(CCLK) Frequency
Serial Data Clock
SCLK Frequency
Conversion Clock
Duty Cycle
Serial Data Clock
Duty Cycle
Conversion Time
MHz (max)
MHz (min)
MHz (max)
Hz (min)
% (min)
% (max)
% (min)
% (max)
(max)
μs (max)
f
SK
5
40
60
40
60
t
C
12-Bit + Sign or 12-Bit
44(t
CK
)
44(t
CK
)
8.8
A
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