參數(shù)資料
型號: ADC12138CIWM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 1.2UF/100VDC METAL POLY CAP
中文描述: 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO28
封裝: SSOP-28
文件頁數(shù): 9/41頁
文件大小: 1085K
代理商: ADC12138CIWM
AC Electrical Characteristics
(Continued)
The following specifications apply for (V
+
= V
+ = V
+ = +5V, V
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
+ = V
+ = +3.3V, V
+ = +2.5V and fully-differential input with fixed 1.250V
common-mode voltage), V
= 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
and V
REF
+
25
, f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified.
Boldface limits apply for T
A
= T
J
=
T
MIN
to T
MAX
;
A
= T
J
= 25C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note
10)
6(t
CK
)
Limits
(Note
11)
6(t
CK
)
7(t
CK
)
1.2
1.4
10(t
CK
)
11(t
CK
)
2.0
2.2
18(t
CK
)
19(t
CK
)
3.6
3.8
34(t
CK
)
35(t
CK
)
6.8
7.0
4944(t
CK
)
988.8
76(t
CK
)
15.2
2(t
CK
)
3(t
CK
)
0.40
0.60
9(t
SK
)
Units
(Limits)
t
A
Acquisition Time
(Note 19)
6 Cycles Programmed
(min)
(max)
μs (min)
μs (max)
(min)
(max)
μs (min)
μs (max)
(min)
(max)
μs (min)
μs (max)
(min)
(max)
μs (min)
μs (max)
(max)
μs (max)
(max)
μs (max)
(min)
(max)
μs (min)
μs (max)
(max)
10 Cycles Programmed
10(t
CK
)
18 Cycles Programmed
18(t
CK
)
34 Cycles Programmed
34(t
CK
)
t
CAL
Self-Calibration Time
4944(t
CK
)
t
AZ
Auto-Zero Time
76(t
CK
)
t
SYNC
Self-Calibration or
Auto-Zero Synchronization
Time from DOR
2(t
CK
)
t
DOR
DOR High Time when CS is Low
Continuously for Read Data and Software
Power Up/Down
CONV Valid Data Time
9(t
SK
)
1.8
μs (max)
t
CONV
8(t
SK
)
8(t
SK
)
1.6
(max)
μs (max)
AC Electrical Characteristics
The following specifications apply for (V
+
= V
+ = V
+ = +5V, V
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
+ = V
+ = +3.3V, V
+ = +2.5V and fully-differential input with fixed 1.250V
common-mode voltage), V
= 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V
and V
REF
+
25
, f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified.
Boldface limits apply for T
A
= T
J
=
T
MIN
to T
MAX
;
A
= T
J
= 25C. (Note 17) (Continued)
Symbol
Parameter
Conditions
Typical
(Note 10)
500
Limits
(Note 11)
700
Units
(Limits)
μs (max)
t
HPU
Hardware Power-Up Time, Time from
PD Falling Edge to EOC Rising Edge
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to
EOC Rising Edge
Access Time Delay from
CS Falling Edge to DO Data Valid
t
SPU
500
700
μs (max)
t
ACC
25
60
ns (max)
A
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