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參數(shù)資料
| 型號： | ADC12132CIMSA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC -20 to 70 |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 30/41頁 |
| 文件大?。?/td> | 1085K |
| 代理商： | ADC12132CIMSA |
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Application Hints
(Continued)
The Multiplexer assignment tables for the ADC12130/2/8
(Table 2 and Table 3) summarize the aforementioned func-
tions for the different versions of A/Ds.
2.1 Biasing for Various Multiplexer Configurations
Figure 11 is an example of biasing the device for
single-ended operation. The sign bit is always low. The digi-
tal output range is 0 0000 0000 0000 to 0 1111 1111 1111.
One LSB is equal to 1 mV (4.1V/4096 LSBs).
For pseudo-differential signed operation, the biasing circuit
shown in Figure 12 shows a signal AC coupled to the ADC.
This gives a digital output range of 4096 to +4095. With a
2.5V reference, as shown, 1 LSB is equal to 610 μV. Al-
though, the ADC is not production tested with a 2.5V refer-
ence, when V
A+
and V
D+
are +5.0V linearity error typically
will not change more than 0.1 LSB (see the curves in the
Typical Electrical Characteristics Section). With the ADC set
to an acquisition time of 10 clock periods, the input biasing
resistor needs to be 600
or less. Notice though that the in-
put coupling capacitor needs to be made fairly large to bring
down the high pass corner. Increasing the acquisition time to
34 clock periods (with a 5 MHz CCLK frequency) would al-
low the 600
to increase to 6k, which with a 1 μF coupling
capacitor would set the high pass corner at 26 Hz. Increas-
ing R, to 6k would allow R
2
to be 2k.
DS012079-38
FIGURE 11. Single-Ended Biasing
A
www.national.com
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