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參數(shù)資料
| 型號： | ADC12081 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold(12位5 MHz可自行校對的管線式帶內(nèi)部采樣和保持功能A/D轉(zhuǎn)換器) |
| 中文描述： | 12位，5兆赫自校準，流水線A / D轉(zhuǎn)換器，內(nèi)置采樣 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 351K |
| 代理商： | ADC12081 |
Timing Diagrams
(Continued)
Functional Description
The ADC12081 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 5 megasamples per second (MSPS). This
device utilizes a proprietary pipeline architecture and algo-
rithm to minimize die size and power consumption. The
ADC12081 uses self-calibration and digital error correction
to maintain accuracy and performance over temperature.
The ADC12081 has an input sample-and-hold amplifier and
internal reference buffer. The analog input and the reference
voltage are converted to differential signals for internal use.
Using differential signals in the analog conversion core re-
duces crosstalk and noise pickup from the digital section and
power supply.
The pipeline conversion core has 15 sequential signal pro-
cessing stages. Each stage receives an analog signal from
the previous stage (called “residue” ) and produces a 1-bit
digital output that is sent to the digital correction module. At
each stage the analog signal received from the previous
stage is compared to an internally generated reference level.
It is then amplified by a factor of 2, and, depending on the
output of the comparator, the internal reference signal may
be subtracted from the amplifier output. This produces the
residue that is passed to the next stage.
The calibration module is activated at power-on or by user
request. During calibration the conversion core is put into a
special mode of operation in order to determine inherent
errors in the analog conversion blocks and to determine
correction coefficients for each digital output bit from the
conversion core and stores these coefficients in RAM. The
digital correction module uses the coefficients in RAM to
convert the raw data bits from the conversion core into the
12-bit digital output code.
Applications Information
1.0 Analog Inputs.
The ADC12081 has two single-ended analog inputs. V
REF
is
the reference input and V
IN
is the signal input.
1.1 Reference Input
The V
REF
input must be driven from an
accurate, stable reference voltage source. of 1.8V to 2.2V,
and bypassed to a clean, quiet point in analog ground.
1.2 Analog Signal Input
The V
input must be driven with
a low impedance signal source that does not add any dis-
tortion to the input signal. The ground reference for the V
IN
input is the V
pin. The V
pin must be connected
to a clean, quiet point in analog ground.
2.0 Digital Inputs
The ADC12081 has four digital inputs. They are CLOCK,
CAL, OE and PD.
2.1 CLOCK
The CLOCK signal drives an internal phase
delay loop to create timing for the ADC. The clock input
should be driven with a stable, low phase jitter TTL level
clock signal in the range of 0.5 to 5 MHz. The trace carrying
the clock signal should be as short as possible. This trace
should not cross any other signal line, analog or digital, not
even at 90. A 100 Ohm resistor should be placed in series
with the CLOCK pin, as close to the pin as possible.
2.2 CAL
The level sensitive CAL input must be pulsed high
for at least three clock cycles to begin ADC calibration. For
best performance, calibration should be performed about ten
seconds after power up, after resetting the ADC, and after
the temperature has changed by more than 50C since the
last calibration was performed.
Calibration should be performed at the same clock fre-
quency that the ADC12081 will be used for conversions to
minimize offset errors. Calibration takes 4000 clock cycles.
Irrelevant data may appear during CAL.
DS100150-22
FIGURE 4. Reset and Calibration Timing
A
www.national.com
11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC12081_02 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit, 5MHz Self-Calibrating, Pipelined A/D Converter with Internal Samble & Hold |
| ADC12081CIVT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12081CIVT/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12081CIVTX | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12081CIVTX NOPB | 制造商:National Semiconductor 功能描述:ADC Single Pipelined 5Msps 12-bit Parallel 32-Pin LQFP T/R |
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