參數(shù)資料
型號: ADC12048CIVF
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter
中文描述: 1-CH 13-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 26/30頁
文件大?。?/td> 635K
代理商: ADC12048CIVF
Analog Application Information
(Continued)
Part Number
Output Voltage
Tolerance
Temperature
Coefficient
±
100ppm/C
±
100ppm/C
±
50ppm/C
±
50ppm/C
±
25ppm/C
±
2ppm/C
LM4041CI-Adj
LM4040AI-4.1
LM4050
LM4121
LM9140BYZ-4.1
Circuit of Figure 20
±
0.5%
±
0.1%
±
0.2%
±
0.1%
±
0.5%
Adjustable
OUTPUT DIGITAL CODE VERSUS ANALOG INPUT
VOLTAGE
The ADC12048’s fully differential 12-bit + sign ADC gener-
ates a two’s complement output that is found by using the
equation shown below:
Round off the result to the nearest integer value between
4096 and 4095.
INPUT CURRENT
At the start of the acquisition window (t
) a charg-
ing current (due to capacitive switching) flows through the
analog input pins (CH0–CH7, ADCIN+ and ADCIN, and the
COM). The peak value of this input current will depend on
the amplitude and frequency of the input voltage applied, the
source impedance and the input switch ON resistance. With
the
MUXOUT+
connected
MUXOUT connected to the ADCIN the on resistance is
typically 2800
. Bypassing the MUX and using just the AD-
CIN+ and ADCIN inputs the on resistance is typically
2500
.
For low impedance voltage sources (
<
1000
for 12 MHz
operation), the input charging current will decay to a value
that will not introduce any conversion errors before the end
of the default sample-and-hold (S/H) acquisition time (9
clock cycles). For higher source impedances (
>
1000
for
12 MHz operation), the S/H acquisition time should be in-
creased to allow the charging current to settle within speci-
fied limits. In asynchronous mode, the acquisition time may
to
the
ADCIN+
and
the
be increased to 15, 47 or 79 clock cycles. If different acqui-
sition times are needed, the synchronous mode can be used
to fully control the acquisition time.
INPUT BYPASS CAPACITANCE
External capacitors (0.01 μF–0.1 μF) can be connected be-
tween the analog input pins (CH0–CH7) and the analog
ground to filter any noise caused by inconductive pickup as-
sociated with long leads.
POWER SUPPLY CONSIDERATIONS
Decoupling and bypassing the power supply on a high reso-
lution ADC is an important design task. Noise spikes on the
V
+ (analog supply) or V
+ (digital supply) can cause con-
version errors. The analog comparator used in the ADC will
respond to power supply noise and will make erroneous con-
version decisions. The ADC is especially sensitive to power
supply spikes that occur during the auto-zero or linearity cali-
bration cycles.
The ADC12048 is designed to operate from a single +5V
power supply. The separate supply and ground pins for the
analog and digital portions of the circuit allow separate exter-
nal bypassing. To minimize power supply noise and ripple,
adequate bypass capacitors should be placed directly be-
tween power supply pins and their associated grounds. Both
supply pins should be connected to the same supply source.
In systems with separate analog and digital supplies, the
ADC should be powered from the analog supply. At least a
10 μF tantalum electrolytic capacitor in parallel with a 0.1 μF
monolithic ceramic capacitor is recommended for bypassing
each power supply. The key consideration for these capaci-
tors is to have low series resistance and inductance. The ca-
DS012387-36
*
Tantalum
**
Ceramic
FIGURE 20. Low Drift Extremely Stable Reference Circuit
A
www.national.com
26
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