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參數(shù)資料
| 型號： | ADC12048CIVF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter |
| 中文描述： | 1-CH 13-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 24/30頁 |
| 文件大?。?/td> | 635K |
| 代理商： | ADC12048CIVF |
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Features and Operating Modes
(Continued)
Once the converter has been calibrated, an arithmetic logic
unit (ALU) uses the offset and linearity correction coefficients
to reduce the conversion offset and linearity errors to within
guaranteed limits.
AUTO-ZERO CYCLE
During an auto-zero cycle, the offset is measured only once
and a correction coefficient is created and stored in an inter-
nal offset register.An auto-zero cycle is initiated by writing an
Auto-Zero command to the ADC12048.
DIGITAL INTERFACE
The digital control signals are CS, RD, WR, RDY and
STDBY. Specific timing relationships are associated with the
interaction of these signals. Refer to the Digital Timing Dia-
grams section for detailed timing specifications. The active
low RDY signal indicates when a certain event begins and
ends. It is recommended that the ADC12048 should only be
accessed when the RDY signal is low. It is in this state that
the ADC12048 is ready to accept a new command. This will
minimize the effect of noise generated by a switching data
bus on the ADC. The only exception to this is when the
ADC12048 is in the standby mode at which time the RDY is
high and the STDBY signal is low. The ADC12048 is in the
standby mode at power up or when a STANDBY command is
issued. A Ful-Cal, Auto-Zero, Reset or Start command will
get theADC12048 out of the standby mode. This may be ob-
served by monitoring the status of the RDY and STDBY sig-
nals. The RDY signal will go low and the STDBY signal high
when the ADC12048 leaves the standby mode.
The following describes the state of the digital control signals
for each programmed event in both 8-bit and 13-bit mode.
RDY should be low before each command is issued except
for the case when the device is in standby mode.
FUL-CAL OR AUTO-ZERO COMMAND
8-bit mode: The first write to the ADC12048 will place the
data in the lower byte of the Configuration register. This byte
must set the HB bit (b
) to allow access to the upper byte of
the Configuration register during the next write cycle. During
the second write cycle, the Ful-Cal or Auto-Zero command
must be issued. The edge of the second write pulse on the
WR pin will force the RDY signal high. At this time the con-
verter begins executing a full calibration or auto-zero cycle.
The RDY signal will automatically go low when the full cali-
bration or auto-zero cycle is done.
13-bit mode: In a single write cycle the Ful-Cal or Auto-Zero
command must be written to theADC12048. The edge of the
WR signal will force the RDY high. At this time the converter
begins executing a full calibration or auto-zero cycle. The
RDY signal will automatically go low when the full calibration
or auto-zero cycle is done.
STARTING A CONVERSION: START COMMAND
In order to completely describe the events associated with
the Start command, both the SYNC-OUT and SYNC-IN
modes must be considered.
SYNC-OUT/Asynchronous
8-bitmode: The first byte written to theADC12048 should set
the MUX channel, the acquisition time and the HB bit. The
second byte should clear the SYNC bit, write the START
command and clear the BW bit. In order to initiate a conver-
sion, two reads must be performed from the ADC12048. The
rising edge of the second read pulse will force the RDY pin
high and begin the programmed acquisition time selected by
bits b
5
and b
4
of the configuration register. The SYNC pin will
go high indicating that a conversion sequence has begun fol-
lowing the end of the acquisition period. The RDY and SYNC
signal will fall low when the conversion is done. At this time
new information, such as a new MUX channel, acquisition
time and operational command can be written into the con-
figuration register or it can remain unchanged. Assuming
that the START command is in the Configuration register, the
previous conversion can be read. The first read places the
lower byte of the conversion result contained in the Data reg-
ister on the data bus. The second read will place the upper
byte of the conversion result stored in the Data register on
the data bus. The rising edge on the second read pulse will
begin another conversion sequence and raise the RDY and
SYNC signals appropriately.
13-bit mode: The MUX channel and the acquisition time
should be set, the SYNC bit cleared and the START com-
mand issued with a single write to theADC12048. In order to
initiate a conversion, a single read must be performed from
the ADC12048. The rising edge of the read signal will force
the RDY signal high and begin the programmed acquisition
time selected by bits b
and b
of the configuration register.
The SYNC pin will go high indicating that a conversion se-
quence has begun following the end of the acquisition pe-
riod. The RDY and SYNC signal will fall low when the con-
version is done. At this time new information, such as a new
MUX channel, acquisition time and operational command
can be written into the configuration register or it can remain
unchanged. With the START command in the Configuration
register, a read from the ADC12048 will place the entire
13-bit conversion result stored in the data register on the
data bus. The rising edge of the read pulse will immediately
force the RDY output high. The SYNC will then go high fol-
lowing the elapse of the programmed acquisition time in the
configuration register’s bits b
5
and b
4
.
SYNC-IN/Synchronous
For the SYNC-IN case, it is assumed that a series of SYNC
pulses at the desired sampling rate are applied at the SYNC
pin of the ADC12048.
8-bitmode: The first byte written to theADC12048 should set
the MUX channel and the HB bit. The second byte should set
the SYNC bit, write the START command and clear the BW
bit.
A rising edge on the SYNC pin or the second rising edge of
two consecutive reads from the ADC12048 will force the
RDY signal high. It is recommended that the action of read-
ing from theADC12048 (not the rising edge of the SYNC sig-
nal) be used to raise the RDY signal. In the SYNC-IN mode,
only the rising edge of the SYNC signal will begin a conver-
sion cycle. The rising edge of the SYNC also ends the acqui-
sition period. The acquisition period begins following a write
cycle containing MUX channel information. The selected
MUX channel is sampled after the rising edge of the WR sig-
nal until the rising edge of the SYNC pulse, at which time the
signal will be held and conversion begins. The RDY signal
will go low when the conversion is done.Anew MUX channel
and/or operational command may be written into the Con-
figuration register at this time, if needed. Two consecutive
read cycles are required to retrieve the entire 13-bit conver-
sion result from the ADC12048’s data register. The first read
will place the lower byte of the conversion result contained in
the Data register on the data bus. The second read will place
the upper byte of the conversion result stored in the Data
A
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| ADC12048 | 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter |
| ADC12048CIV | 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC12048CIVF/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B PLUS SIGN 216KHz 8CH SAMPLING ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12048CIVF/NOPB | 制造商:Texas Instruments 功能描述:A/D Converter (A-D) IC |
| ADC12048EVAL | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter |
| ADC1205 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit Plus Sign mP Compatible A/D Converters |
| ADC1205BCJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 13-Bit |
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