參數(shù)資料
型號: ADC10061CIWM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold
中文描述: 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20
封裝: SOP-20
文件頁數(shù): 8/14頁
文件大小: 333K
代理商: ADC10061CIWM
Timing Diagrams
Functional Description
The ADC10061, ADC10062 and ADC10064 digitize an ana-
log input signal to 10 bits accuracy by performing two
lower-resolution “flash” conversions. The first flash conver-
sion provides the six most significant bits (MSBs) of data,
and the second flash conversion provides the four least sig-
nificant bits LSBs).
Figure 3 is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the bot-
tom of the string of resistors are 16 resistors, each of which
has a value 1/1024 the resistance of the whole resistor
string. These lower 16 resistors (the
LSB Ladder
) therefore
have a voltage drop of 16/1024, or 1/64 of the total reference
voltage (V
V
) across them. The remainder of the
resistor string is made up of eight groups of eight resistors
connected in series. These comprise the
MSB Ladder
. Each
section of the MSB Ladder has
1
8
of the total reference volt-
age across it, and each of the LSB resistors has 1/64 of the
DS011020-9
FIGURE 1. Mode 1. The conversion time (t
CONV
) is set by the internal timer.
DS011020-10
FIGURE 2. Mode 2 (RD Mode). The conversion time (t
) includes the
sampling time and is determined by the internal timer.
www.national.com
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