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參數(shù)資料
| 型號： | ADC10030 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold |
| 中文描述： | 10位，30 MSPS的，125毫瓦的A / D內(nèi)部采樣與保持器 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大小： | 417K |
| 代理商： | ADC10030 |
Applications Information
(Continued)
6.0 DYNAMIC PERFORMANCE
The ADC10030 is ac tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
ac performance, isolating the ADC clock from any digital cir-
cuitry should be done with adequate buffers, as with a clock
tree. See Figure 8
Meeting dynamic specifications is also dependent upon
keeping digital noise out of the input, as mentioned in Sec-
tions 1.0 and 5.0.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails.
For proper operation, all inputs should not go
more than 300 mV beyond the supply pins. Exceeding these
limits on even a transient basis can cause faulty or erratic
operation. It is not uncommon for high speed digital circuits
(e.g., 74F and 74AC devices) to exhibit undershoot that goes
more than a volt below ground. A resistor of 50
to 100
in
series with the offending digital input will usually eliminate
the problem.
Care should be taken not to overdrive the inputs of the
ADC10030 (or any device) with a device that is powered
from supplies outside the range of the ADC10030 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers has to charge for
each conversion, the more instantaneous digital current is
required from V
I/O and DGND I/O. These large charging
current spikes can couple into the analog section, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital ground planes will reduce this
problem on the board. Buffering the digital data outputs (with
an 74F541, for example) may be necessary if the data bus to
be driven is heavily loaded. Dynamic performance can also
be improved by adding series resistors of 47
at each digital
output.
Driving the V
+ F pin or the V
F pin with devices
that can not source or sink the current required by the
ladder.
As mentioned in section 2.0, be careful to see that
any driving devices can source sufficient current into the
V
+ F pin and sink sufficient current from the V
F pin.
If these pins are not driven with devices than can handle the
required current, they will not be held stable and the con-
verter output will exhibit excessive noise.
Using a clock source with excessive jitter.
This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. The use of simple
gates with RC timing is generally inadequate.
Using the same voltage source for V
and digital logic.
As mentioned in section 3.0, V
should use the same power
source used by V
A
, but should be decoupled from V
A
.
DS101064-22
FIGURE 8. Isolating the ADC Clock
from Digital Circuitry
A
www.national.com
16
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