參數(shù)資料
型號(hào)： ADC0820
廠商： National Semiconductor Corporation
英文描述： 8-Bit High Speed μP Compatible A/D Converter with Track/Hold Function(8位高速μP兼容A/D轉(zhuǎn)換器帶跟蹤/保持功能)
中文描述： CMOS、高速、8位A/D轉(zhuǎn)換器，帶有采樣/保持功能
文件頁(yè)數(shù)： 4/22頁(yè)
文件大?。?/td> 472K
代理商： ADC0820
DC Electrical Characteristics
The following specifications apply for V
CC
=5V, unless otherwise specified.
Boldface limits apply from T
MIN
to T
MAX
; all other
limits T
A
=T
J
=25C.
Parameter
Conditions
ADC0820CCJ
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820BCWM
ADC0820CCWM, ADC0820CIWM
Typ
Tested
(Note 6)
Limit
(Note 7)
2.0
3.5
0.8
1.5
0.005
0.1
0.3
50
170
0.005
Limit
Units
Typ
Tested
Limit
(Note 7)
2.0
3.5
0.8
1.5
1
3
200
1
Design
Limit
(Note 8)
Design
Limit
(Note 8)
2.0
3.5
0.8
1.5
1
3
200
1
(Note 6)
V
IN(1)
, Logical “1”
Input Voltage
V
IN(0)
, Logical “0”
Input Voltage
I
IN(1)
, Logical “1”
Input Current
V
CC
=5.25V
CS , WR , RD
Mode
CS , WR , RD
Mode
V
V
V
V
μA
μA
μA
μA
V
CC
=4.75V
V
IN(1)
=5V; CS , RD
V
IN(1)
=5V; WR
V
IN(1)
=5V; Mode
V
IN(0)
=0V; CS , RD , WR ,
Mode
V
CC
=4.75V, I
OUT
=360 μA;
DB0–DB7, OFL , INT
V
CC
=4.75V, I
OUT
=10 μA;
DB0–DB7, OFL , INT
V
CC
=4.75V, I
OUT
=1.6 mA;
DB0–DB7, OFL , INT , RDY
V
OUT
=5V; DB0–DB7, RDY
V
OUT
=0V; DB0–DB7, RDY
V
OUT
=0V; DB0–DB7, OFL
INT
V
OUT
=5V; DB0–DB7, OFL ,
INT , RDY
CS =WR =RD =0
0.005
0.1
50
0.005
I
IN(0)
, Logical “0”
Input Current
V
OUT(1)
, Logical “1”
Output Voltage
2.4
2.8
2.4
V
4.5
4.6
4.5
V
V
OUT(0)
, Logical “0”
Output Voltage
I
OUT
, TRI-STATE
Output Current
I
SOURCE
, Output
Source Current
I
SINK
, Output Sink
Current
I
CC
, Supply Current
0.4
0.34
0.4
V
0.1
0.1
12
9
14
3
0.1
0.1
12
9
14
0.3
0.3
7.2
5.3
8.4
3
μA
μA
mA
mA
mA
3
6
4.0
7
3
6
4.0
7
7.5
15
7.5
13
15
mA
AC Electrical Characteristics
The following specifications apply for V
CC
=5V, t
r
=t
f
=20 ns, V
REF
(+)=5V, V
REF
()=0V and T
A
=25C unless otherwise speci-
fied.
Typ
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
2.5
Parameter
Conditions
(Note 6)
Units
t
CRD
, Conversion Time for RD
Mode
t
ACC0
, Access Time (Delay from
Falling Edge of RD to Output
Valid)
t
CWR-RD
, Conversion Time for
WR-RD Mode
t
WR
, Write Time
Pin 7 = 0, Figure 2
1.6
μs
Pin 7 = 0, Figure 2
t
CRD
+20
t
CRD
+50
ns
Pin 7 = V
CC
; t
WR
= 600 ns,
t
RD
=600 ns; Figures 3, 4
Pin 7 = V
CC
; Figures 3, 4
(Note 4) See Graph
Pin 7 = V
CC
; Figures 3, 4
(Note 4) See Graph
Pin 7 = V
CC
, t
RD
<
t
I
; Figure 3
C
L
=15 pF
1.52
μs
Min
Max
Min
600
ns
μs
ns
50
t
RD
, Read Time
600
t
ACC1
, Access Time (Delay from
Falling Edge of RD to Output
Valid)
190
280
ns
C
L
=100 pF
210
320
ns
www.national.com
4
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