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參數(shù)資料
| 型號： | ADC08200 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D Converter |
| 中文描述： | 8位，20 MSPS的200 MSPS的，1.05毫瓦/ MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 537K |
| 代理商： | ADC08200 |
Applications Information
(Continued)
where t
r
is the clock rise time and t
is the propagation rate
of the signal along the trace, the
CLOCK
pin should be a.c.
terminated with a series RC to ground such that the resisitor
value is equal to the characteristic impedance of the clock
line and the capacitor value is
where "L" is the line length in inches, t
prop
is the signal
propagation rate down the clock line and Z
o
is the charac-
teristic impedance of the clock line. Typical t
is about 150
ps/inch on FR-4 board material. For FR-4 board material, the
value of C becomes
Where L is the length of the clock line in inches.
This termination should be located as close as possible to,
but within one centimeter of, the ADC08200 clock pin.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are es-
sential to ensure accurate conversion. A combined analog
and digital ground plane should be used.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise
because of the skin effect. Total surface area is more impor-
tant than is total ground plane volume. Capacitive coupling
between the typically noisy digital circuitry and the sensitive
analog circuitry can lead to poor performance that may seem
impossible to isolate and remedy. The solution is to keep the
analog circuitry well separated from the digital circuitry.
High power digital components should not be located on or
near a straight line between the ADC or any linear compo-
nent and the power supply area as the resulting common
return current path could cause fluctuation in the analog
input “ground” return of the ADC.
Generally, analog and digital lines should cross each other at
90 to avoid getting digital noise into the analog path. In high
frequency systems, however, avoid crossing analog and
digital lines altogether. Clock lines should be isolated from
ALL other lines, analog AND digital. Even the generally
accepted 90 crossing should be avoided as even a little
coupling can cause problems at high frequencies. Best per-
formance at high frequencies is obtained with a straight
signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected be-
tween the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
Figure 5
gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed together away from any digital compo-
nents.
6.0 DYNAMIC PERFORMANCE
The ADC08200 is ac tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must exhibit less than 2 ps
(rms) of jitter. For best ac performance, isolating the ADC
clock from any digital circuitry should be done with adequate
buffers, as with a clock tree. See
Figure 6
.
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal. The
clock signal can also introduce noise into the analog path.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails.
For proper operation, all inputs should not go
more than 300 mV below the ground pins or 300 mV above
the supply pins. Exceeding these limits on even a transient
basis may cause faulty or erratic operation. It is not uncom-
mon for high speed digital circuits (e.g., 74F and 74AC
20017936
FIGURE 5. Layout Example
20017937
FIGURE 6. Isolating the ADC Clock from Digital
Circuitry
A
www.national.com
16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC08200_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sample-and-Hold |
| ADC08200CIMT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC08200CIMT/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC08200CIMTX | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC08200CIMTX/HAPB | 制造商:Texas Instruments 功能描述: |
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