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參數(shù)資料
| 型號： | ADC0819CCV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer |
| 中文描述： | 19-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 279K |
| 代理商： | ADC0819CCV |
Electrical Characteristics
(Continued)
The following specifications apply for V
CC
e
5V, V
REF
e
5V,
w
2 CLK
e
2.097 MHz unless otherwise specified.
Boldface limits
apply from T
MIN
to T
MAX
;
all other limits T
A
e
T
J
e
25
§
C.
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Parameter
Conditions
Units
DIGITAL AND DC CHARACTERISTICS
(Continued)
V
OUT(1)
, Logical ‘‘1’’
Output Voltage (Min)
V
CC
e
4.75V
I
OUT
eb
360
m
A
I
OUT
eb
10
m
A
V
CC
e
5.25V
I
OUT
e
1.6 mA
V
OUT
e
0V
V
OUT
e
5V
V
OUT
e
0V
2.4
4.5
2.4
4.5
V
V
V
OUT(0)
, Logical ‘‘0’’
Output Voltage (Max)
0.4
0.4
V
I
OUT
, TRI-STATE Output
Current (Max)
b
0.01
0.01
b
3
3
b
3
3
m
A
m
A
I
SOURCE
, Output Source
Current (Min)
b
14
b
6.5
b
6.5
mA
I
SINK
, Output Sink Current (Min)
I
CC
, Supply Current (Max)
I
REF
(Max)
V
OUT
e
V
CC
CS
e
1, V
REF
Open
V
REF
e
5V
16
8.0
8.0
mA
1
2.5
2.5
mA
0.7
1
1
mA
AC CHARACTERISTICS
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Parameter
Conditions
Typical
(Note 6)
Units
w
2 CLK
,
w
2
Clock Frequency
MIN
0.70
1.0
MHz
MAX
4.0
2.0
2.1
S
CLK
, Serial Data Clock
Frequency
MIN
5.0
KHz
MAX
1000
525
525
T
C
, Conversion Process Time
MIN
Not Including MUX
Addressing and
Analog Input
Sampling Times
26
26
w
2
cycles
MAX
32
32
t
ACC
, Access Time Delay From CS
Falling Edge to DO Data Valid
MIN
1
w
2
cycles
MAX
3
t
SET-UP
, Minimum Set-up Time of CS Falling
Edge to S
CLK
Rising Edge
t
HCS
, CS Hold Time After the Falling
Edge of S
CLK
t
CS
, Total CS Low Time
4/
w
2CLK
a
1
2 S
CLK
sec
0
ns
MIN
t
set-up
a
8/S
CLK
sec
MAX
t
CS
(min)
a
26/
w
2CLK
sec
t
HDI
, Minimum DI Hold Time from
S
CLK
Rising Edge
t
HDO
, Minimum DO Hold Time from S
CLK
Falling Edge
0
0
ns
R
L
e
30k,
C
L
e
100 pF
10
ns
t
SDI
, Minimum DI Set-up Time to S
CLK
Rising Edge
200
400
ns
t
DDO
, Maximum Delay From S
CLK
Falling Edge to DO Data Valid
R
L
e
30k,
C
L
e
100 pF
R
L
e
3k,
C
L
e
100 pF
180
200
250
ns
t
TRI
, Maximum DO Hold Time,
(CS Rising edge to DO TRI-STATE)
90
150
150
ns
3
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