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參數(shù)資料
| 型號(hào)： | ADC08161 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference(500ns帶S/H功能和2.5V帶隙參考的A/D轉(zhuǎn)換器) |
| 中文描述： | 500納秒的A / D轉(zhuǎn)換器與S /高功能和2.5V帶隙基準(zhǔn)（500ns的帶采樣/功能和2.5V的帶隙參考的的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 12/15頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | ADC08161 |
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Application Information
(Continued)
tween 0 and 3/16 of V
(V
= V
V
), the esti-
mator decoder instructs the comparator multiplexer to select
the eight tap points between 8/256 and 2/8 of V
and con-
nects them to the eight flash comparators. The first flash
conversion is now performed, producing the five MSBs of
data.
The remaining three LSBs are generated next using the
same eight comparators that were used for the first flash
conversion. As determined by the results of the MSB flash, a
voltage from the MSB Ladder equivalent to the magnitude of
the five MSBs is subtracted from the analog input voltage as
the upper switch is moved from position one to position two.
The resulting remainder voltage is applied to the eight flash
comparators and, with the lower switch in position two, com-
pared with the eight tap points from the LSB Ladder.
By using the same eight comparators for both flash conver-
sions, the number of comparators needed by the multi-step
converter is significantly reduced when compared to stan-
dard half-flash techniques.
Voltage Estimator errors as large as 1/16 of V
(16 LSBs)
will be corrected since the flash comparators are connected
to ladder voltages that extend beyond the range specified by
the Voltage Estimator. For example, if 7/16 V
<
V
<
9/16 V
the Voltage Estimator’s comparators tied to the
tap points below 9/16 V
will output “1”s (000111). This is
decoded by the estimator decoder to “10”. The eight flash
comparators will be placed at the MSB Ladder tap points be-
tween
3
8
V
and
5
8
V
. The overlap of 1/16 V
on
each side of the Voltage Estimator’s span will automatically
correct an error of up to 16 LSBs (16 LSBs = 312.5 mV for
V
= 5V). If the first flash conversion determines that the
input voltage is between
3
8
V
and 4/8 V
LSB/2, the
Voltage Estimator’s output code will be corrected by sub-
tracting “1”. This results in a corrected value of “01”. If the
first flash conversion determines that the input voltage is be-
tween 8/16 V
LSB/2 and
5
8
V
, the Voltage Estima-
tor’s output code remains unchanged.
After correction, the 2-bit data from both the Voltage Estima-
tor and the first flash conversion are decoded to produce the
five MSBs. Decoding is similar to that of a 5-bit flash con-
verter since there are 32 tap points on the MSB Ladder.
However, 31 comparators are not needed since the Voltage
Estimator places the eight comparators along the MSB Lad-
der where reference tap voltages are present that fall above
and below the magnitude of V
. Comparators are not
needed outside this selected range. If a comparator’s output
is a “0”, all comparators above it will also have outputs of “0”
and if a comparator’s output is a “1”, all comparators below it
will also have outputs of “1”.
2.0 DIGITAL INTERFACE
The ADC08161 has two basic interface modes which are se-
lected by connecting the
MODE
pin to a logic high or low.
2.1 RD Mode
With a logic low applied to the
MODE
pin, the converter is set
to
Read
mode. In this configuration (Figure 1), a complete
conversion is done by pulling RD low, and holding low, until
the conversion is complete and output data appears. This
typically takes 655 ns. The INT (interrupt) line goes low at
the end of conversion. A typical delay of 50 ns is needed be-
tween the rising edge of CS (after the end of a conversion)
and the start of the next conversion (by pulling RD low). The
RDY output goes low after the falling edge of CS and goes
high at the end-of-conversion. It can be used to signal a pro-
cessor that the converter is busy or serve as a system Trans-
fer Acknowledge signal.
2.2 RD Mode Pipelined Operation
Applications that require shorter RD pulse widths than those
used in the
Read
mode as described above can be achieved
by setting RD’s width between 200 ns–400 ns (Figure 5). RD
pulse widths outside this range will create conversion linear-
ity errors. These errors are caused by exercising internal in-
terface logic circuitry using CS and/or RD during a conver-
sion.
When RD goes low, a conversion is initiated and the data
from the previous conversion is available on the DB0–DB7
outputs. Reading DB0–DB7 for the first two times after
power-up produces random data. The data will be valid dur-
ing the third RD pulse that occurs after the first conversion.
2.3 WR-RD (WR then RD ) Mode
The ADC08161 is in the
WR-RD mode
with the
MODE
pin
tied high. A conversion starts on the rising edge of the WR
signal. There are two options for reading the output data
which relate to interface timing. If an interrupt-driven scheme
is desired, the user can wait for the INT output to go low be-
fore reading the conversion result (Figure 3). Typically, INT
will go low 690 ns, maximum, after WR’s rising edge. How-
ever, if a shorter conversion time is desired, the processor
need not wait for INT and can exercise a read after only 350
ns (Figure 2). If RD is pulled low before INT goes low, INT
will immediately go low and data will appear at the outputs.
This is the fastest operating mode (t
≤
t
) with a conver-
sion time, including data access time, of 560 ns. Allowing
100 ns for reading the conversion data and the delay be-
tween conversions gives a total throughput time of 660 ns
(throughput rate of 1.5 MHz).
2.4 WR-RD Mode with Reduced Interface System
Connection
CS and RD can be tied low, using only WR to control the
start of conversion for applications that require reduced digi-
tal interface while operating in the
WR-RD mode
(Figure 4).
Data will be valid approximately 705 ns following WR’s rising
edge.
3.0 REFERENCE INPUTS
The ADC08161’s two V
inputs are fully differential and
define the zero to full-scale input range of the A to D con-
verter. This allows the designer to vary the span of the ana-
log input since this range will be equivalent to the voltage dif-
ference between V
and V
. Transducers that have
outputs that minimum output voltages above GND can also
be compensated by connecting V
to a voltage that is
equal to this minimum voltage. By reducing V
(V
=
V
–V
) to less than 5V, the sensitivity of the converter
can be increased (i.e., if V
= 2.5V, then 1 LSB = 9.8 mV).
The reference arrangement also facilitates ratiometric opera-
tion and in may cases the power supply can be used for
transducer power as well as the V
REF
source. Ratiometric
operation is achieved by connecting V
to GND and con-
necting V
and a transducer’s power supply input to V
+
.
The ADC08161s accuracy degrades when V
REF+
–|V
REF
| is
less than 2.0V.
The voltage at V
sets the input level that produces a
digital output of all zeroes. Through V
IN
is not itself differen-
www.national.com
12
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