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參數(shù)資料
| 型號： | ADC08161 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference(500ns帶S/H功能和2.5V帶隙參考的A/D轉(zhuǎn)換器) |
| 中文描述： | 500納秒的A / D轉(zhuǎn)換器與S /高功能和2.5V帶隙基準(zhǔn)（500ns的帶采樣/功能和2.5V的帶隙參考的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 246K |
| 代理商： | ADC08161 |
Application Information
1.0 FUNCTIONAL DESCRIPTION
The ADC08161 performs an 8-bit analog-to-digital conver-
sion using a multi-step flash technique. The first flash gener-
ates the five most significant bits (MSBs) and the second
flash generates the three least significant bits (LSBs). Figure
6 shows the major functional blocks of the ADC08161
multi-step flash converter. It consists of an over-encoded
2
1
2
-bit Voltage Estimator, an internal DAC with two different
voltage spans, a 3-bit half-flash converter and a comparator
multiplexer.
The resistor string near the center of the block diagram in
Figure 6 forms the internal main DAC. Each of the eight re-
sistors at the bottom of the string is equal to 1/256 of the total
string resistance. These resistors form the
LSB Ladder
and
have a voltage drop of 1/256 of the total reference voltage
(V
V
) across them. The remaining resistors make
up the
MSB Ladder
. They are made up of eight groups of
four resistors connected in series. Each MSB Ladder section
has
1
8
of the total reference voltage across it. Within a given
MSB Ladder section, each of the MSB resistors has 8/256,
or
1
3
2 of the total reference voltage across it. Tap points are
found between all of the resistors in both the MSB and LSB
Ladders. Through the Comparator Multiplexer these tap
points can be connected, in groups of eight, to the eight com-
parators shown at the right of Figure 6 This function pro-
vides the necessary reference voltages to the comparators
during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of Figure 6 form the Volt-
age Estimator. The estimator DAC connected between
V
and V
generates the reference voltages for the
six Voltage Estimator comparators. These comparators per-
form a very low resolution A/D conversion to obtain an “esti-
mate” of the input voltage. This estimate is then used to con-
trol the Comparator Multiplexer, connecting the appropriate
MSB Ladder section to the eight flash comparators. Only 14
comparators, six in the Voltage Estimator and eight in the
flash converter, are needed to achieve the full eight-bit reso-
lution, instead of 32 comparators that would be needed by
traditional half-flash methods.
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the es-
timator DAC. The estimator decoder then selects one of the
groups of tap points along the MSB Ladder. These eight tap
points are then connected to the eight flash comparators.
For example, if the analog input signal applied to V
IN
is be-
DS011149-17
FIGURE 6. Block Diagram of the ADC08161 Multi-Step Flash Architecture
www.national.com
11
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| ADC08161CIWM | 功能描述:IC ADC 500NS S/H 2.5V REF 20SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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