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參數(shù)資料
| 型號： | ADC081500CIYB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP128 |
| 封裝： | MS-026BFB, LQFP-128 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大小： | 830K |
| 代理商： | ADC081500CIYB |
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1.0 Functional Description
(Continued)
TABLE 3. Register Addresses
(Continued)
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
Ch
Dh
Eh
Fh
Reserved
Reserved
Reserved
Reserved
1.4 REGISTER DESCRIPTION
Three write-only registers provide several control and con-
figuration options in the Extended Control Mode. These reg-
isters have no effect when the device is in the Normal
Control Mode. Each register description below also shows
the Power-On Reset (POR) state of each control bit.
Configuration Register
Addr: 1h (0001b)
W only (0xB2FF)
D15
1
D14
0
D13
1
D12
DCS
D11
DCP
D10
nDE
D9
OV
D8
OE
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Bit 15
Bit 14
Bit 13
Bit 12
Must be set to 1b
Must be set to 0b
Must be set to 1b
DCS:Duty Cycle Stabilizer. When this bit is
set to 1b , a duty cycle stabilzation circuit is
applied to the clock input. When this bit is set
to 0b the stabilzation circuit is disabled.
POR State: 1b
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set
to 0b, the DCLK edges are time-aligned with
the data bus edges ("0 Phase"). When this
bit is set to a 1b, the DCLK edges are placed
in the middle of the data bit-cells ("90
Phase").
POR State: 0b
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Double
Data Rate) mode whereby a data word is
output with each rising and falling edge of
DCLK. When this bit is set to a 1b, data bus
clocking follows the SDR (single data rate)
mode whereby each data word is output with
either the rising or falling edge of DCLK , as
determined by the OutEdge bit.
POR State: 0b
Bit 11
Bit 10
Bit 9
OV: Output Voltage. This bit determines the
LVDS outputs’ voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mV
P-P
is used. When this bit is set to 0b, the
reduced output amplitude of 510 mV
P-P
is
used.
POR State: 1b
OE: Output Edge. This bit selects the DCLK
edge with which the data words transition in
the SDR mode and has the same effect as
the OutEdge pin in the normal control mode.
When this bit is 1, the data outputs change
with the rising edge of DCLK+. When this bit
is 0, the data output change with the falling
edge of DCLK+.
POR State: 0b
Must be set to 1b.
Bit 8
Bits 7:0
Input Offset
Addr: 2h (0010b)
W only (0x007F)
D15
(MSB)
D14
D13
D12
Offset Value
D11
D10
D9
D8
(LSB)
D7
Sign
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Bits 15:8
Input Offset Value. The input offset of the
ADC is adjusted linearly and monotonically
by the value in this field. 00h provides a
nominal zero offset, while FFh provides a
nominal 45 mV of offset. Thus, each code
step provides 0.176 mV of offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
Bit 7
Bit 6:0
A
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADC081500CIYB/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC081500DEV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| ADC081500EVAL | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| ADC0816 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit レP Compatible A/D Converters with 16-Channel Multiplexer |
| ADC0816_07 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit レP Compatible A/D Converters with 16-Channel Multiplexer |
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