參數(shù)資料
型號(hào)： ADC0805LCN
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： ADC
英文描述： 8-Bit uP Compatible A/D Converters
中文描述： 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP20
封裝： PLASTIC, DIP-20
文件頁(yè)數(shù)： 27/41頁(yè)
文件大?。?/td> 1118K
代理商： ADC0805LCN
Functional Description
(Continued)
Note 18:
The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack.
Note 19:
All address used were arbitrarily chosen.
The standard control bus signals of the 8080 CS, RD and
WR) can be directly wired to the digital control inputs of the
A/D and the bus timing requirements are met to allow both
starting the converter and outputting the data onto the data
bus. A bus driver should be used for larger microprocessor
systems where the data bus leaves the PC board and/or
must drive capacitive loads larger than 100 pF.
4.1.1 Sample 8080A CPU Interfacing Circuitry and
Program
The following sample program and associated hardware
shown in Figure 12 may be used to input data from the con-
verter to the INS8080A CPU chip set (comprised of the
INS8080A microprocessor, the INS8228 system controller
and the INS8224 clock generator). For simplicity, the A/D is
controlled as an I/O device, specifically an 8-bit bi-directional
port located at an arbitrarily chosen port address, E0. The
TRI-STATE output capability of the A/D eliminates the need
for a peripheral interface device, however address decoding
is still required to generate the appropriate CS for the con-
verter.
It is important to note that in systems where the A/D con-
verter is 1-of-8 or less I/O mapped devices, no address de-
coding circuitry is necessary. Each of the 8 address bits (A0
to A7) can be directly used as CS inputs— one for each I/O
device.
4.1.2 INS8048 Interface
The INS8048 interface technique with the ADC0801 series
(see Figure 13) is simpler than the 8080A CPU interface.
There are 24 I/O lines and three test input lines in the 8048.
With these extra I/O lines available, one of the I/O lines (bit
0 of port 1) is used as the chip select signal to the A/D, thus
eliminating the use of an external address decoder. Bus con-
trol signals RD, WR and INT of the 8048 are tied directly to
the A/D. The 16 converted data words are stored at on-chip
RAM locations from 20 to 2F (Hex). The RD and WR signals
are generated by reading from and writing into a dummy ad-
dress, respectively. A sample interface program is shown
below.
SAMPLE PROGRAM FOR
Figure 12
ADC0801–INS8080A CPU INTERFACE
DS005671-99
A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ADC0805LCN/B+ 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit
ADC0805LCN/NOPB 功能描述:IC ADC 8BIT MPU COMPAT 20-DIP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:-
ADC0806 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter
ADC08060 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter
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