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參數(shù)資料
| 型號(hào)： | ADC0804 |
| 廠商： | Intersil, Corp. |
| 元件分類： | 串行ADC |
| 英文描述： | 8-Bit, Microprocessor-Compatible A/D Converters |
| 中文描述： | 8位微處理器兼容的A/D轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 250K |
| 代理商： | ADC0804 |
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6-16
Driving the Data Bus
This CMOS A/D, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuItry, which is tied to the data
bus, will add to the total capacitive loading, even in three-
state (high-impedance mode). Back plane busing also
greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to han-
dle this problem. Basically, the capacitive loading of the data
bus slows down the response time, even though DC specifi-
cations are still met. For systems operating with a relatively
slow CPU clock frequency, more time is available in which to
establish proper logic levels on the bus and therefore higher
capacitive loads can be driven (see Typical Performance
Curves).
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock-extending circuits (6800).
Finally, if time is short and capacitive loading is high,
external bus drivers must be used. These can be three-state
buffers (low power Schottky is recommended, such as the
74LS240 series) or special higher-drive-current products
which are designed as bus drivers. High-current bipolar bus
drivers with PNP inputs are recommended.
Power Supplies
Noise spikes on the V+ supply line can cause conversion
errors as the comparator will respond to this noise. A
low-inductance tantalum filter capacitor should be used
close to the converter V+ pin, and values of 1
μ
F or greater
are recommended. If an unregulated voltage is available in
the system, a separate 5V voltage regulator for the converter
(and other analog circuitry) will greatly reduce digital noise
on the V+ supply. An lCL7663 can be used to regulate such
a supply from an input as low as 5.2V.
Wiring and Hook-Up Precautions
Standard digital wire-wrap sockets are not satisfactory for
breadboarding with this A/D converter. Sockets on PC
boards can be used. All logic signal wires and leads should
be grouped and kept as far away as possible from the analog
signal leads. Exposed leads to the analog inputs can cause
undesired digital noise and hum pickup; therefore, shielded
leads may be necessary in many applications.
A single-point analog ground should be used which is separate
from the logic ground points. The power supply bypass capaci-
tor and the self-clockIng capacitor (if used) should both be
returned to digital ground. Any V
REF
/2 bypass capacitors, ana-
log input filter capacitors, or input signal shielding should be
returned to the analog ground point. A test for proper grounding
is to measure the zero error of the A/D converter. Zero errors in
excess of
1
/
4
LSB can usually be traced to improper board
layout and wiring (see Zero Error for measurement). Further
information can be found in Application Note AN018.
Testing the A/D Converter
There are many degrees of complexity associated with testing
an A/D converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEDs to
display the resulting digital output code as shown in Figure 18.
For ease of testing, the V
REF
/2 (pin 9) should be supplied
with 2.560V and a V+ supply voltage of 5.12V should be
used. This provides an LSB value of 20mV.
If a full scale adjustment is to be made, an analog input volt-
age of 5.090V (5.120 - 1
1
/
2
LSB) should be applied to the
V
IN(+)
pin with the V
IN(-)
pin grounded. The value of the
V
REF
/2 input voltage should be adjusted until the digital out-
put code is just changing from 1111 1110 to 1111 1111. This
value of V
REF
/2 should then be used for all the tests.
The digital-output LED display can be decoded by dividing the 8
bits into 2 hex characters, one with the 4 most-significant bits
(MS) and one with the 4 least-significant bits (LS). The output is
then interpreted as a sum of fractions times the full scale voltage:
.
For example, for an output LED display of 1011 0110, the
MS character is hex B (decimal 11) and the LS character is
hex (and decimal) 6, so:
.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
ADC0802 - ADC0804
WR
RD
CS
INTR
CLK IN
V
IN
(-)
V
IN
(+)
DGND
V
REF
/2
AGND
DB
1
DB
2
DB
0
DB
4
DB
5
DB
3
DB
7
DB
6
CLK R
V+
10K
5V (V
REF
)
10
μ
F
+
DATA
OUTPUTS
START
ANALOG
INPUTS
150pF
N.O.
MSB
LSB
FIGURE 17. FREE-RUNNING CONNECTION
V
OUT
--------
---------
+
5.12
(
)
V
=
START
V
IN
(+)
DGND
2.560V
V
REF
/2
AGND
10
μ
F
TANTALUM
150pF
N.O.
0.1
μ
F
0.1
μ
F
5.120V
5V
1.3k
LEDs
(8)
(8)
MSB
LSB
10k
+
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
ADC0802-
ADC0804
FIGURE 18. BASIC TESTER FOR THE A/D
VOUT
------
---------
+
5.12
(
)
3.64V
=
=
ADC0802, ADC0803, ADC0804
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